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参数资料
| 型号： | ADMC201 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 13/16页 |
| 文件大小： | 193K |
| 代理商： | ADMC201 |
ADMC201
REV. A
–13–
T able VII. SYSCT RL Analog Input Channel Selection
Bit 3
Bit 4
Channels Converted
Mode
0
0
1
1
0
1
0
1
V, W (Default)
V, W, AUX
U, V, W
U, V, W, AUX
T wo-/T hree-Phase
T wo-/T hree-Phase
T hree-/T hree-Phase
T hree-/T hree-Phase
Bit 0, 1 Auxiliary Channel Selection.
Bit 3
Channel U Conversion Enable. If Bit 3 is set to 1, then
Channel U will be converted along with V, W and/or
AUX . T his bit selects three-/three-phase mode.
Bit 4
Aux Channel Conversion Enable. If Bit 4 is set to
1, then the AUX input will be converted along with
the channels V, W and/or U.
Bit 5
If Bit 5 = 1, then the external clock will be divided by
two to derive the system clock. If the external clock
frequency is greater than 12.5 MHz, then this bit must
be set.
Bit 6
Park Interrupt Enable. T his bit allows interrupts to
be generated when the Park rotation is completed.
Bit 7
ADC Interrupt Enable. T his bit allows interrupts to
be generated when the analog-to-digital conversion
process is complete.
Bit 8
IRQ
Pin Format—Edge or Level Interrupt Selection.
If Bit 8 is set to 0, then an interrupt will cause a
pulse of one system clock to be generated on the
IRQ
pin. If Bit 8 is set to 1, then an interrupt
causes the
IRQ
output to go LOW (logic 0). T he
IRQ
output pin will remain LOW until the SYSST AT
register is read.
Bit 10
If Bit 10 is set to 1, then the reverse Park transforma-
tion will be formed in 3/3 mode. For Forward
transformations, this bit must be set to 1.
T able V. System Control (SYSCT RL) Registers
RESET
Default
Bit
Function
0
1
3
Auxiliary Channel Selection
Auxiliary Channel Selection
Enables U Channel Conversion
(1 = Enable) T wo-/T hree-Phase Mode
Enables AUX Channel Conversion
(0 = Disable, 1 = Enable)
Divide External Clock by 2
(0 = No, 1 = Yes)
Park Interrupt Enable
ADC Interrupt Enable
(0 = Disable, 1 = Enable)
IRQ
Pin Format (Edge or Level Based
Interrupt Requests) (0 = Edge)
Reverse Rotation (0 = 2/3, 1 = 3/3)
Forward Rotation (1 = Enable)
0
0
0
4
0
5
0
0
6
7
0
8
0
0
10
T able VI. SYSCT RL Auxiliary Channel Selection
Bit 0
Bit 1
Auxiliary Channels Converted
0
0
1
1
0
1
0
1
AUX 0
AUX 1
AUX 2
AUX 3
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