参数资料
型号: ADMC201
厂商: Analog Devices, Inc.
英文描述: Motion Coprocessor(动作协处理器)
中文描述: 运动协处理器(动作协处理器)
文件页数: 2/16页
文件大小: 193K
代理商: ADMC201
ADMC201–SPECIFICATIONS
Parameter
REV. A
–2–
ADMC201AP
Units
Conditions/Comments
ANALOG-T O-DIGIT AL CONVERT ER
1
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Match
Full-Scale Error
Full-Scale Error Match
Conversion T ime/Channel
Signal-to-Noise Ratio (SNR)
2
Channel-to-Channel Isolation
T wo-/T hree-Phase Mode
T hree-/T hree-Phase Mode
ANALOG INPUT S
Input Voltage Level
Analog Input Current
Input Capacitance
T RACK AND HOLD
Aperture Delay
Aperture T ime Delay Match
SHA Acquisition T ime
Droop Rate
REFERENCE INPUT
Voltage Level
Reference Input Current
REFERENCE OUT PUT
Voltage Level
Voltage Level T olerance
Drive Capability
LOGIC
V
IL
V
IH
V
OL
V
Input Leakage Current
T hree-State Leakage Current
Input Capacitance
12-BIT PWM T IMERS
Resolution
Programmable Deadtime Range
Programmable Deadtime Increments
Programmable Pulse Deletion Range
Programmable Deletion Increments
Minimum PWM Frequency
11
±
2
±
2
±
5
4
±
6
4
40
60
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
System CLK Cycles
dB min
T wos Complement Data Format
Integral Nonlinearity
No Missing Codes Guaranteed
Any Channel
Between Channels
Any Channel
Between Channels
f
IN
= 600 Hz Sine Wave, f
SAMPLE
= 55 kHz, 600 Hz
–58
–55
dB max
dB max
Sine Wave Applied to Unselected Channels
0–5
100
10
Volts
μ
A max
pF typ
200
20
20
5
ns max
ns max
System CLK Cycles
mV/ms max
Any Channel
Between Channels
2.5
50
V dc
μ
A max
2.5
±
5
±
200
Volts
% max
μ
A max
Full Load
0.8
2.0
0.4
4.5
1
1
20
V max
V min
V max
V min
μ
A max
μ
A max
pF typ
I
SINK
= 400
μ
A, V
DD
= 5 V
I
SOURCE
= 20
μ
A, V
DD
= 5 V
12
0–10.08
2
0–10.16
1
1.5
Bits
μ
s
System CLK Cycles
μ
s
System CLK Cycle
kHz
160 ns
80 ns
Resolution Varies with PWM Switching Frequency
(10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits,
5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre-
quencies are Available with Lower Resolution
Park & Clarke T ransformation
VECT OR T RANSFORMAT ION
Radius Error
Angular Error
Reverse T ransformation T ime
Forward T ransformation T ime
EX T ERNAL CLOCK INPUT
Range
0.7
30
37
40
% max
arc min max
System CLK Cycles
System CLK Cycles
6.25–25
MHz
If > 12.5 MHz, T hen It Is Necessary to Divide Down
via SYSCT RL Register
INT ERNAL SYST EM CLOCK
Range
POWER SUPPLY CURRENT
I
DD
6.25–12.5
MHz
20
mA max
NOT ES
1
Measurements made with external reference.
2
T ested with PWM Switching Frequency of 25 kHz.
Specifications subject to change without notice.
(V
DD
= +5 V
6
5%; AGND = DGND = 0 V; REFIN= 2.5 V;
External Clock = 12.5 MHz; T
A
= –40
8
C to +85
8
C unless otherwse noted)
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