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参数资料
| 型号： | ADMC201 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 7/16页 |
| 文件大小： | 193K |
| 代理商： | ADMC201 |
ADMC201
REV. A
–7–
PWM T IME R BLOCK OVE RVIE W
T he PWM timers have 12-bit resolution and support program-
mable pulse deletion and deadtime. T he ADMC201 generates
three center-based signals A, B and C based upon user-supplied
duty cycles values. T he three signals are then complemented
and adjusted for programmable deadtime to produce the six
outputs. T he ADMC201 PWM master switching frequency can
range from 2.5 kHz to 20 kHz, when using a 10 MHz system
clock. T he master frequency selection is set as a fraction of the
PWMT M register. If the system clock is 10 MHz, then the
minimum edge resolution available is 100 ns.
T he output format of the PWM block is active LO. T here is an
external input to the PWM timers (ST OP) that will disable all
six outputs within one system clock when the input is HIGH.
T he ADMC201 has a PWM Synchronization output
(PWMSY NC) which brings out the master switching frequency
from the PWM timers. T he width of the PWMSYNC pulse is
equal to one system clock cycle. For example, if the system clock
is 10 MHz, the PWMSYNC width would be equal to 100 ns.
PWM Master Switching Period Selection
T he switching time is set by the PWMT M register which should
be loaded with a value equal to the system clock frequency
divided by the desired master switching frequency. For ex-
ample, if the desired switching frequency is 8 kHz and the sys-
tem clock frequency is 10 MHz, then the PWMT M register
should be loaded with 1250 (10 MHz/8 kHz). T he PWMCHA,
PWMCHB and PWMCHC registers are loaded with the
desired on-time and their values would be calculated as a ratio
of the PWMT M register value. Note: Desired Pulse Density =
(PWMCHx register)/( PWMT M register).
T he beginning of each PWM cycle is marked by the PWMSYNC
signal. New values of PWMCHA, PWMCHB and PWMCHC
must all be loaded into their respective registers at least four sys-
tem clock cycles before the beginning of a new PWM cycle. All
three registers must be updated for any of them to take effect.
New PWM on/off times are calculated during these four clock
cycles and therefore the PWMCHA, PWMCHB and PWMCHC
registers must be loaded before this time. If this timing require-
ment is not met, then the PWM outputs may be invalid during
the next PWM cycle.
PWM E xample
T he following example uses a system clock speed of 10 MHz.
T he desired PWM master switching frequency is 8 kHz and the
desired on-time for the timers A, B and C are 25%, 50% and
10% respectively. T he values for the PWMCHA, PWMCHB
and PWMCHC registers must be calculated as ratios of the
PWMT M register (1250 in this example). T o achieve these
duty cycles, load the PWMCHA register with 313 (1250
×
0.25), PWMCHB with 625 (1250
×
0.5) and PWMCHC with
125 (1250
×
0.1).
Programmable Deadtime
With perfectly complemented PWM drive signals and nonideal
switching characteristics of the power devices, both transistors
in a particular leg might be switched on at the same time, result-
ing in either a power supply trip, inverter trip or device destruc-
tion. In order to prevent this, a delay must be introduced
between the complemented signal edges. For example, the ris-
ing edge of AP occurs before the falling edge of A, and the fall-
ing edge of the complemented A occurs after the rising edge of
A. T his capability is known as programmable deadtime.
T he ADMC201 programmable deadtime value is loaded into
the 7-bit PWMDT register, in which the LSB is set to zero in-
ternally, which means the deadtime value is always divisible by
two. With a 10 MHz system clock, the 0–126 range of values in
PWMDT yield a range of deadtime values from 0
μ
s to 12.6
μ
s
in 200 ns steps. Figure 6 shows PWM timer A with a program-
mable deadtime of PWMDT .
PWMCHA - PWMDT
A
PWMTM
AP
PWMCHA + PWMDT
Figure 6. Programmable Deadtime Example
Pulse Deletion
T he pulse deletion feature prevents a pulse from being gener-
ated when the user-specified duty cycle results in a pulse dura-
tion shorter than the user-specified deletion value. T he pulse
deletion value is loaded into the 7-bit register PWMPD. When
the user-specified on-time for a channel would result in a calcu-
lated pulse width less than the value specified in the PWMPD
register, then the PWM outputs for that channel would be set to
full off (0%) and its prime to full on (100%). T his is valid for
A, AP, B, BP, C and CP. T his feature would be used in an en-
vironment where the inverter’s power transistors have a mini-
mum switching time. If the user-specified duty cycle would
result in a pulse duration shorter than the minimum switching
time of the transistors, then pulse deletion should be used to
prevent this occurrence. With a 10 MHz system clock, the 0–
127 range of values in PWMPD yield a range of deadtime values
from 0
μ
s to 12.7
μ
s in 100 ns steps.
E xternal PWM Shutdown
T here is an external input pin (ST OP) to the PWM timers that
will disable all six outputs when it goes HIGH. When the ST OP
pin goes HIGH, the PWM timer outputs will all go HIGH
within one system clock cycle. When the ST OP pin goes LOW,
the PWM timer outputs are re-enabled within one system clock
cycle. If external PWM shutdown isn't required, tie the ST OP
pin LOW.
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| ADMC201AP | 制造商:Analog Devices 功能描述: |
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