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参数资料
| 型号： | ADMC201 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 6/16页 |
| 文件大小： | 193K |
| 代理商： | ADMC201 |
ADMC201
REV. A
–6–
Interrupt Driven Method
Interrupts can be used to indicate the end of conversion for a
group of channels. Before beginning any A/D conversions, Bit 7
of the SYSCT RL register must be set to 1 to enable A/D con-
version interrupts. T hen, when an A/D conversion is complete,
an interrupt will be generated. After an interrupt is detected,
Bit 0 of the SYSST AT register must be checked to determine if
the A/D converter was the source. Reading the SYSST AT reg-
ister automatically clears the interrupt flag bits.
Software T iming Method
An alternative method is to use the DSP or microcontroller to
keep track of the amount of time elapsed between CONVST
and the expected completion time (n
×
t
CONV
).
Reading Results
T he 11-bit A/D conversion results for channels U, V, W and
AUX are stored in the ADCU, ADCV, ADCW and ADCAUX
registers respectively. T he twos complement data is left justified
and the LSB is set to zero. T he relationship between input volt-
age and output coding is shown in Figure 5.
01 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
OUTPUT
CODE
FULL-SCALE
TRANSITION
0V
2.5
5V–1LSB
INPUT VOLTAGE
FS = 5V
LSB =
5V
2048
Figure 5. Transfer Function
Sample and Hold
After powering up the ADMC201, bring the
RESET
pin low for
a minimum of two clock cycles in order to enable A/D conver-
sions. Before initiating the first conversion (CONVST ) after a
reset, the SHA time of 20 system clock cycles must occur. A
conversion is initiated by bringing CONVST high for a mini-
mum of one system clock cycle. T he SHA goes into hold mode
at the falling edge of clock.
Following completion of the A/D conversion process, a mini-
mum of 20 system clock cycles are required before initiating an-
other conversion in order to allow the sample and hold circuitry
to reacquire the input signals.
If a CONVST is initiated before the 20 clock cycles have
elapsed, the embedded control sequencer will delay conversion
until this requirement is met.
ANALOG INPUT BLOCK
T he ADMC201 contains an 11-bit resolution, successive approxi-
mation analog-to-digital (A/D) converter with twos complement
output data format. T he analog input range is
±
2.5 V (0 V–5 V)
with a 2.5 V offset as defined by REFIN. T he on-chip 2.5 V
±
5% reference is utilized by connecting the REFOUT pin to the
REFIN pin.
T he input stage to the A/D converter is a four channel SHA
which allows the four channels (U, V, W and AUX ) to be held
simultaneously and then sequentially digitized. T he auxiliary
input (AUX ) is fed by a four channel multiplexer that allows the
channels AUX 0, AUX 1, AUX 2 and AUX 3 to be individually
converted along with the primary channels U, V and W. T he
auxiliary inputs are ideal for reading slower changing variables
such as bus voltage and temperature. T he A/D conversion time
is determined by the system clock frequency, which can range
from 6.25 MHz to 12.5 MHz. T he Sample and Hold (SHA)
acquisition time is 20 system clock cycles and is independent of
the number of channels sampled and/or digitized. Forty system
clock cycles are required to complete each A/D conversion. T he
analog channel sampling is flexible and is programmable
through the SYSCT RL register. T he minimum number of
channels per conversion is two. T he throughput time of the
analog acquisition block can be calculated as follows:
t
AA
=
t
SHA
+
(
n
×
t
CONV
)
where
t
AA
= analog acquisition time,
n = # channels,
t
SHA
= SHA acquisition time (20
×
system clock period),
t
CONV
= conversion time (40
×
system clock period) per channel.
A/D Conversions are initiated via the CONVST pin. A syn-
chronizing pulse (PWMSYNC) is provided at the beginning of
each PWM cycle. T his pulse can be used to synchronize the
A/D conversion process to the PWM switching frequency.
Operating the A/D Converter
T he A/D converter can be set up to convert a sequence of chan-
nels as defined in the SYSCT RL register (see T able VI). T he
default channel select mode after
RESET
is to convert channels
V and W only. T his is two-/three-phase mode. T hree-/three-
phase mode converts channels U, V, W, and/or AUX . T hree-/
three-phase mode is selected by writing a 1 to Bit 3 of the
SYSCT RL register. After the conversion process is complete,
the channels can be read in any order.
T here are two methods that can be used to indicate when the
A/D conversions are completed and the data is ready: interrupt
driven and software timing.
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