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| 型号： | ADP1823ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32LFCSP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 720kHz |
| 占空比： | 90% |
| 电源电压： | 3.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
| 其它名称： | ADP1823ACPZ-R7DKR |
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ADP1823
THEORY OF OPERATION
The ADP1823 is a dual, synchronous, PWM buck controller
capable of generating output voltages down to 0.6 V and output
currents in the tens of amps. The switching of the regulators is
interleaved for reduced current ripple. It is ideal for a wide
range of applications, such as DSP and processor core I/O
supplies, general-purpose power in telecommunications,
medical imaging, gaming, PCs, set-top boxes, and industrial
controls. The ADP1823 controller operates directly from 3.7 V
to 20 V, and the power stage input voltage range is 1 V to 24 V,
which applies directly to the drain of the high-side external
power MOSFET. It includes fully integrated MOSFET gate
drivers and a linear regulator for internal and gate drive bias.
The ADP1823 operates at a fixed 300 kHz or 600 kHz switching
frequency. The ADP1823 can also be synchronized to an external
clock to switch at up to 1 MHz per channel. The ADP1823
includes soft start to prevent inrush current during startup, as
well as a unique adjustable lossless current limit.
The ADP1823 offers flexible tracking for startup and shutdown
sequencing. It is specified over the ?40 ° C to +125 ° C temperature
range and is available in a space-saving, 5 mm × 5 mm,
32-lead LFCSP.
INPUT POWER
The ADP1823 is powered from the IN pin up to 20 V. The
internal low dropout linear regulator, VREG, regulates the IN
voltage down to 5 V. The control circuits, gate drivers, and
external boost capacitors operate from the LDO output. Tie
the PV pin to VREG and bypass VREG with a 1 μ F or greater
capacitor.
The ADP1823 phase shifts the switching of the two step-down
converters by 180 ° , thereby reducing the input ripple current.
The phase shift reduces the size and cost of the input capacitors.
The input voltage should be bypassed with a capacitor close to
Capacitor section). In addition, a minimum 0.1 μF ceramic
capacitor should be placed as close as possible to the IN pin.
The VREG output is sensed by the undervoltage lockout
(UVLO) circuit to be certain that enough voltage headroom
is available to run the controllers and gate drivers. As VREG
rises above about 2.7 V, the controllers are enabled. The IN
voltage is not directly monitored by UVLO. If the IN voltage is
insufficient to allow VREG to be above the UVLO threshold,
the controllers are disabled but the LDO continues to operate.
The LDO is enabled whenever either EN1 or EN2 is high, even
if VREG is below the UVLO threshold.
If the desired input voltage is between 3.7 V and 5.5 V, connect
IN directly to the VREG pin and the PV pin, and drive LDOSD
high to disable the internal regulator. The ADP1823 requires
Otherwise, it should be grounded or left open. LDOSD has an
internal 100 kΩ pull-down resistor.
Although IN is limited to 20 V, the switching stage can run from
up to 24 V, and the BST pins can go to 30 V to support the gate
drive. Dissipation on the ADP1823 can be limited by running IN
from a low voltage rail while operating the switches from the high
voltage rail.
START-UP LOGIC
The ADP1823 features independent enable inputs for each
channel. Drive EN1 or EN2 high to enable their respective
controllers. The LDO starts when either channel is enabled.
When both controllers are disabled, the LDO is disabled and
the IN quiescent current drops to about 10 μ A. For automatic
startup, connect EN1 and/or EN2 to IN. The enable pins are
20 V compliant, but they sink current through an internal
100 kΩ resistor when the EN pin voltage exceeds about 5 V.
INTERNAL LINEAR REGULATOR
The internal linear regulator, VREG, is low dropout, which means
it can regulate its output voltage close to the input voltage.
VREG powers up the internal control and provides bias for
the gate drivers. It is guaranteed to have more than 100 mA of
output current capability, which is sufficient to handle the gate
drive requirements of typical logic threshold MOSFETs driven
at up to 1 MHz. VREG should always be bypassed with a 1 μ F
or greater capacitor.
Because the LDO supplies the gate drive current, the output of
VREG is subject to sharp transient currents as the drivers switch
and the boost capacitors recharge during each switching cycle.
The LDO has been optimized to handle these transients without
overload faults. Due to the gate drive loading, using the VREG
output for other auxiliary system loads is not recommended.
The LDO includes a current limit well above the expected
maximum gate drive load. This current limit also includes a
short-circuit foldback to further limit the VREG current in the
event of a fault.
OSCILLATOR AND SYNCHRONIZATION
The ADP1823 internal oscillator can be set to either 300 kHz or
600 kHz. Drive the FREQ pin low for 300 kHz; drive it high for
600 kHz. The oscillator generates a start clock for each switching
phase and generates the internal ramp voltages for the PWM
modulation.
The SYNC input is used to synchronize the converter switching
frequency to an external signal. The SYNC input should be
driven with twice the desired switching frequency, as the SYNC
input is divided by 2, and the resulting phases are used to clock
the two channels alternately.
that the voltage at VREG and PV be limited to no more than 5.5
V, which is the only application where the LDOSD pin is used.
Rev. D | Page 13 of 32
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1823-EVAL | 功能描述:BOARD EVAL FOR ADP1823 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
| ADP1828 | 制造商:AD 制造商全称:Analog Devices 功能描述:Synchronous Buck PWM, Step-Down, DC-to-DC Controller |
| ADP1828ACPZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 20LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1828-BL1-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
| ADP1828-BL2-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
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