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| 型号： | ADP1823ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32LFCSP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 720kHz |
| 占空比： | 90% |
| 电源电压： | 3.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
| 其它名称： | ADP1823ACPZ-R7DKR |
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ADP1823
MOSFET DRIVERS
The DH1 and DH2 pins drive the high-side switch MOSFETs.
These boosted 5 V gate drivers are powered by bootstrap capacitor
circuits. This configuration allows the high-side, N-channel
MOSFET gate to be driven above the input voltage, allowing
full enhancement and a low voltage drop across the MOSFET.
The bootstrap capacitors are connected from the SW pins to
their respective BST pins. The bootstrap Schottky diodes from
the PV pin to the BST pins recharge the bootstrap capacitors every
time the SW nodes go low. Use a bootstrap capacitor value
greater than 100× the high-side MOSFET input capacitance.
In practice, the switch node can run up to 24 V of input voltage,
and the boost nodes can operate more than 5 V above this to
allow full gate drive. The IN pin can be run from 3.7 V to 20 V,
which can provide an advantage, for example, in the case of high
frequency operation from very high input voltage. Dissipation on
the ADP1823 can be limited by running IN from a lower voltage
rail while operating the switches from the high voltage rail.
The switching cycle is initiated by the internal clock signal. The
high-side MOSFET is turned on by the DH driver, and the SW
node goes high, pulling up on the inductor. When the internally
generated ramp signal crosses the COMP pin voltage, the switch
MOSFET is turned off and the low-side synchronous rectifier
MOSFET is turned on by the DL driver. Active break-before-
make circuitry, as well as a supplemental fixed dead time, are
used to prevent cross-conduction in the switches.
The DL1 and DL2 pins provide gate drive for the low-side
MOSFET synchronous rectifiers. Internal circuitry monitors
the external MOSFETs to ensure break-before-make switching
to prevent cross-conduction. An active dead time reduction
circuit reduces the break-before-make time of the switching to
limit the losses due to current flowing through the synchronous
rectifier body diode.
The PV pin provides power to the low-side drivers. It is limited
to 5.5 V maximum input and should have a local decoupling
capacitor.
The synchronous rectifiers are turned on for a minimum time
of about 200 ns on every switching cycle to sense the current.
This minimum on time and the nonoverlap dead times put a limit
on the maximum high-side switch duty cycle based on the selected
switching frequency. Typically, this is about 90% at 300 kHz
switching, and at 1 MHz switching, it reduces to about 70%
maximum duty cycle.
Because the two channels are 180° out of phase, if one is operating
around 50% duty cycle, it is common for it to jitter when the
other channel starts switching. The magnitude of the jitter depends
somewhat on layout, but it is difficult to avoid in practice.
When the ADP1823 is disabled, the drivers shut off the external
CURRENT LIMIT
The ADP1823 employs a unique, programmable, cycle-by-cycle
lossless current-limit circuit that uses a small, ordinary, inexpensive
resistor to set the threshold. Every switching cycle, the synchro-
nous rectifier turns on for a minimum time and the voltage
drop across the MOSFET R DSON is measured during the off
cycle to determine whether the current is too high.
This measurement is done by an internal current-limit
comparator and an external current-limit set resistor. The
resistor is connected between the switch node (that is, the
drain of the rectifier MOSFET) and the CSL pin. The CSL pin,
which is the inverting input of the comparator, forces 50 μA
through the resistor to create an offset voltage drop across it.
When the inductor current is flowing in the MOSFET rectifier,
its drain is forced below PGND by the voltage drop across its
R DSON . If the R DSON voltage drop exceeds the preset drop on the
external resistor, the inverting comparator input is similarly
forced below PGND and an overcurrent fault is flagged.
The normal transient ringing on the switch node is ignored for
100 ns after the synchronous rectifier turns on; therefore, the
overcurrent condition must also persist for 100 ns in order for a
fault to be flagged.
When an overcurrent event occurs, the overcurrent comparator
prevents switching cycles until the rectifier current has decayed
below the threshold. The overcurrent comparator is blanked
for the first 100 ns of the synchronous rectifier cycle to prevent
switch node ringing from falsely tripping the current limit. The
ADP1823 senses the current limit during the off cycle. When
the current-limit condition occurs, the ADP1823 resets the
internal clock until the overcurrent condition disappears. The
ADP1823 suppresses the start clock cycles until the overload
condition is removed. At the same time, the SS capacitor is
discharged through a 6 kΩ resistor. The SS input is an auxiliary
positive input of the error amplifier, so it behaves like another
voltage reference. The lowest reference voltage wins.
Discharging the SS voltage causes the converter to use a lower
voltage reference when switching is allowed again. Therefore,
as switching cycles continue around the current limit, the output
looks roughly like a constant current source due to the rectifier
limit, and the output voltage droops as the load resistance
decreases. In the event of a short circuit, the short-circuit
output current is the current limit set by the R CL resistor and
is monitored cycle by cycle. When the overcurrent condition is
removed, operation resumes in soft start mode.
In the event of a short circuit, the ADP1823 also offers a
technique for implementing a current-limit foldback with the
section for more information.
MOSFETs, so that the SW node becomes three-stated or
changes to high impedance.
Rev. D | Page 15 of 32
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1823-EVAL | 功能描述:BOARD EVAL FOR ADP1823 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
| ADP1828 | 制造商:AD 制造商全称:Analog Devices 功能描述:Synchronous Buck PWM, Step-Down, DC-to-DC Controller |
| ADP1828ACPZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 20LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1828-BL1-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
| ADP1828-BL2-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
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