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| 型号： | ADP1823ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32LFCSP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 720kHz |
| 占空比： | 90% |
| 电源电压： | 3.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
| 其它名称： | ADP1823ACPZ-R7DKR |
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ADP1823
Because of the finite output current drive of the error amplifier,
C I needs to be less than 10 nF. If it is larger than 10 nF, choose a
larger R TOP and recalculate R Z and C I until C I is less than 10 nF.
The soft start period ends when the voltage on the soft start pin
reaches 0.6 V. Substituting 0.6 V for V SS and solving for the
number of RC time constants
C HF =
?
0 . 6 V = 0 . 8 V ? 1 ? e 90 kΩ ( C SS )
?
?
?
Because C HF << C I , combining Equation 29 and Equation 39 yields
1
(44)
π f SW R Z
Next calculate the feedforward capacitor, C FF . Assuming R FF <<
R TOP , then Equation 28 is simplified to
?
t SS = 1.386 RC SS
Because R = 90 kΩ,
t SS
?
?
(49)
(50)
f Z 2 =
1
2 π C FF R TOP
(45)
C SS = t SS × 8 μF/s
where t SS is the desired soft start time in seconds.
(51)
Solving C FF in Equation 45 yields
VOLTAGE TRACKING
C FF =
1
2 π R TOP f Z 2
(46)
The ADP1823 includes a tracking feature that prevents an
output voltage from exceeding a master voltage. This feature is
especially important when the ADP1823 is powering separate
where f Z2 is obtained from Equation 40 or Equation 41.
The feedforward resistor, R FF , can be calculated by combining
Equation 30 and Equation 39.
power supply voltages on a single integrated circuit, such as the
core and I/O voltages of a DSP or microcontroller. In these
cases, improper sequencing can cause damage to the load.
R FF =
1
π C FF f SW
(47)
The ADP1823 tracking input is an additional positive input to
the error amplifier. The feedback voltage is regulated to the lower of
the 0.6 V reference or the voltage at TRK; therefore, a lower
Check that the calculated component values are reasonable. For
instance, capacitors smaller than about 10 pF should be avoided.
In addition, the ADP1823 error amplifier has finite output
current drive; therefore, R Z values less than 3 kΩ and C I values
greater than 10 nF should be avoided. If necessary, recalculate the
compensation network with a different starting value of R TOP . If
R Z is too small and C I is too big, start with a larger value of R TOP .
This compensation technique should yield a good working
solution.
In general, aluminum electrolytic capacitors have high ESR;
therefore, a Type II compensation is adequate. However, if several
aluminum electrolytic capacitors are connected in parallel,
producing a low effective ESR, Type III compensation is needed. In
addition, ceramic capacitors have very low ESR, on the order of
a few milliohms; therefore, Type III compensation is needed for
ceramic output capacitors. Type III compensation offers better
performance than Type II in terms of more low frequency gain
and more phase margin and less high frequency gain at the
crossover frequency.
voltage on TRK limits the output voltage. This feature allows
implementation of two different types of tracking: coincident
tracking, where the output voltage is the same as the master
voltage until the master voltage reaches regulation, or ratiometric
tracking, where the output voltage is limited to a fraction of the
master voltage.
In all tracking configurations, the master voltage should be
higher than the slave voltage.
Note that the soft start time setting of the master voltage should
be longer than the soft start of the slave voltage. This forces the
rise time of the master voltage to be imposed on the slave voltage.
If the soft start setting of the slave voltage is longer, the slave
comes up more slowly and the tracking relationship is not seen
at the output. The slave channel should still have a soft start
capacitor to give a small but reasonable soft start time to protect
in case of a restart after a current-limit event.
V OUT
R TOP
SOFT START
The ADP1823 uses an adjustable soft start to limit the output
voltage ramp-up period, thus limiting the input inrush current.
COMP
FB
R BOT
The soft start is set by selecting the capacitor, C SS , from SS1 and
SS2 to GND. The ADP1823 charges C SS to 0.8 V through an
internal 90 kΩ resistor. The voltage on the soft start capacitor
ERROR
AMPLIFIER
TRK
0.6V
SS
R TRKT
MASTER
VOLTAGE
while it is charging is
?
? 1 ? e RC SS
?
?
?
V CSS = 0 . 8 V
?
t
?
?
(48)
DETAIL VIEW OF
ADP1823
Figure 30. Voltage Tracking
R TRKB
Rev. D | Page 22 of 32
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1823-EVAL | 功能描述:BOARD EVAL FOR ADP1823 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
| ADP1828 | 制造商:AD 制造商全称:Analog Devices 功能描述:Synchronous Buck PWM, Step-Down, DC-to-DC Controller |
| ADP1828ACPZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 20LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1828-BL1-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
| ADP1828-BL2-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
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