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| 型号： | ADP1823ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32LFCSP |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 720kHz |
| 占空比： | 90% |
| 电源电压： | 3.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
| 其它名称： | ADP1823ACPZ-R7DKR |
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ADP1823
SETTING THE CURRENT LIMIT
V IN
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set through the current-limit resistor, R CL .
The current sense pins, CSL1 and CSL2, source 50 μA through
their respective R CL . This current source creates an offset voltage of
R CL multiplied by the 50 μA CSL current. When the drop across
ADP1823
DH
DL
CSL
M1
M2
R LO
L
R HI
V OUT
C OUT
the low-side MOSFET R DSON is equal to or greater than this
offset voltage, the ADP1823 flags a current-limit event.
Because the CSL current and the MOSFET R DSON vary over
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum R DSON of the MOSFET at its highest expected
temperature, and the minimum CSL current.
Figure 25. Short-Circuit Current Foldback Scheme
Because the buck converters are usually running fairly high
current, PCB layout and component placement may affect the
current-limit setting. An iteration of the R CL or R LO and R HI
values may be required for a particular board layout and
MOSFET selection. If alternate MOSFETs are substituted at
some point in production, these resistor values may also need
an iteration.
FEEDBACK VOLTAGE DIVIDER
R CL =
I LPK R DSON ( MAX )
44 μA
(15)
The output regulation voltage is set through the feedback voltage
divider. The output voltage is reduced through the voltage divider
where I LPK is the peak inductor current.
In addition, the ADP1823 offers a technique for implementing
a current-limit foldback in the event of a short circuit with the
use of an additional resistor, as shown in Figure 25. Resistor R LO
is largely responsible for setting the foldback current limit during a
short circuit, and R HI is mainly responsible for setting up the
normal current limit. R LO is lower than R HI . These current-limit
sense resistors can be calculated by
and drives the FB feedback input. The regulation threshold at
FB is 0.6 V. The maximum input bias current into FB is 100 nA.
For a 0.15% degradation in regulation voltage and with 100 nA
bias current, the low-side resistor, R BOT , needs to be less than 9 kΩ,
which results in 67 μA of divider current. For R BOT , use 1 kΩ to
10 kΩ. A larger value resistor can be used but results in a reduction
in output voltage accuracy due to the input bias current at the
FB pin, whereas lower values cause increased quiescent current
consumption. Choose R TOP to set the output voltage by using
? 44 μ A
? V FB
?
R TOP = R BOT ? OUT
? ?
R LO =
R HI =
I PKFOLDBACK R DSON ( MAX )
44 μ A
V OUT
R DSON ( MAX )
I LPK
R LO
(16)
(17)
the following equation:
? V ?
? V FB ?
where:
R TOP is the high-side voltage divider resistance.
(18)
where:
I PKFOLDBACK is the desired short-circuit peak inductor current limit.
I LPK is the peak inductor current limit during normal operation
R BOT is the low-side voltage divider resistance.
V OUT is the regulated output voltage.
V FB is the feedback regulation threshold, 0.6 V.
(also used in Equation 15).
Rev. D | Page 18 of 32
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1823-EVAL | 功能描述:BOARD EVAL FOR ADP1823 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
| ADP1828 | 制造商:AD 制造商全称:Analog Devices 功能描述:Synchronous Buck PWM, Step-Down, DC-to-DC Controller |
| ADP1828ACPZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 20LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1828-BL1-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
| ADP1828-BL2-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
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