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参数资料
| 型号： | ADSP-21478KBCZ-3A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/76页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARK 300MHZ 196CSPBGA |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 300MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.30V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA，CSPBGA |
| 供应商设备封装： | 196-CSPBGA（12x12） |
| 包装： | 托盘 |
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Rev. C
|
Page 19 of 76
|
July 2013
TDI
I (ipu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO
O/T
High-Z
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (ipu)
Test Mode Select (JTAG). Used to control the test state machine.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the device.
TRST
I (ipu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the processor.
EMU
O (O/D, ipu)
High-Z
Emulation Status. Must be connected to the Analog Devices DSP Tools product
line of JTAG emulators target board connector only.
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the startup clock frequency.
Note that the operating frequency can be changed by programming the PLL
multiplier and divider in the PMCTL register at any time after the core comes out
of reset. The allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It
configures the processors to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the processors to use the external clock source
such as an external clock oscillator. CLKIN may not be halted, changed, or
operated below the specified frequency.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
RESETOUT/RUNRSTIN I/O (ipu)
Reset Out/Running Reset In. The default setting on this pin is reset out. This pin
also has a second function as RUNRSTIN which is enabled by setting bit 0 of the
RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
BOOT_CFG2–0
I
Boot Configuration Select. These pins select the boot mode for the processor.
The BOOT_CFG pins must be valid before RESET (hardware and software) is de-
asserted.
The BOOT_CFG2 pin is only available on the 196-lead package.
Table 11. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on
Page 70.
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| ADSP-21478KCPZ-1A | 功能描述:IC DSP SHARK 200MHZ 88LFCSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-1A | 功能描述:IC DSP SHARC 200MHZ LP 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-ENG | 制造商:Analog Devices 功能描述:SHARC PROCESSOR - Trays |
| ADSP-21479 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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