参数资料
型号: ADSP-21478KBCZ-3A
厂商: Analog Devices Inc
文件页数: 36/76页
文件大小: 0K
描述: IC DSP SHARK 300MHZ 196CSPBGA
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,DPI,EBI/EMI,I²C,SPI,SPORT,UART/USART
时钟速率: 300MHz
非易失内存: ROM(4Mb)
芯片上RAM: 3Mb
电压 - 输入/输出: 3.30V
电压 - 核心: 1.30V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 196-LFBGA,CSPBGA
供应商设备封装: 196-CSPBGA(12x12)
包装: 托盘
Rev. C
|
Page 41 of 76
|
July 2013
Serial Ports
In slave transmitter mode and master receiver mode, the maxi-
mum serial port frequency is fPCLK/8. In master transmitter
mode and slave receiver mode, the maximum serial port clock
frequency is fPCLK/4.
To determine whether communication is possible between two
devices at clock speed, n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 34. Serial Ports—External Clock
88-Lead LFCSP Package
All Other Packages
Unit
Parameter
Min
Max
Min
Max
Timing Requirements
tSFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)
42.5
ns
tHFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)
42.5
ns
tSDRE
1
Receive Data Setup Before Receive SCLK
4
2.5
ns
tHDRE
1
Receive Data Hold After SCLK
4
2.5
ns
tSCLKW
SCLK Width
(tPCLK × 4) ÷ 2 – 1.5
ns
tSCLK
SCLK Period
tPCLK × 4
ns
Switching Characteristics
tDFSE
2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or
Receive Mode)
15
ns
tHOFSE
2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or
Receive Mode)
22ns
tDDTE
2
Transmit Data Delay After Transmit SCLK
15
ns
tHDTE
2
Transmit Data Hold After Transmit SCLK
2
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
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