- 您现在的位置：买卖IC网 > PDF目录19395 > ADSP-21478KBCZ-3A (Analog Devices Inc)IC DSP SHARK 300MHZ 196CSPBGA PDF资料下载
参数资料
| 型号： | ADSP-21478KBCZ-3A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/76页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARK 300MHZ 196CSPBGA |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 300MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.30V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA，CSPBGA |
| 供应商设备封装： | 196-CSPBGA（12x12） |
| 包装： | 托盘 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
Rev. C
|
Page 12 of 76
|
July 2013
Shift Register
The shift register can be used as a serial to parallel data con-
verter. The shift register module consists of an 18-stage serial
shift register, 18-bit latch, and three-state output buffers. The
shift register and latch have separate clocks. Data is shifted into
the serial shift register on the positive-going transitions of the
shift register serial clock (SR_SCLK) input. The data in each
flip-flop is transferred to the respective latch on a positive-going
transition of the shift register latch clock (SR_LAT) input.
The shift register’s signals can be configured as follows.
The SR_SCLK can come from any of the SPORT0–7 SCLK
outputs, PCGA/B clock, any of the DAI pins (1–8), and one
dedicated pin (SR_SCLK).
The SR_LAT can come from any of SPORT0–7 frame sync
outputs, PCGA/B frame sync, any of the DAI pins (1–8),
and one dedicated pin (SR_LAT).
The SR_SDI input can from any of SPORT0–7 serial data
outputs, any of the DAI pins (1–8), and one dedicated pin
(SR_SDI).
Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must
come from same source except in the case of where SR_SCLK
comes from PCGA/B or SR_SCLK and SR_LAT come from
PCGA/B.
If SR_SCLK comes from PCGA/B, then SPORT0–7 generates
the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT
come from PCGA/B, then SPORT0–7 generates the
SR_SDI signal.
I/O PROCESSOR FEATURES
The I/O processor provides up to 65 channels of DMA as well as
an extensive set of peripherals.
DMA Controller
The DMA controller operates independently and invisibly to
the processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions. DMA
transfers can occur between the processor’s internal memory
and its serial ports, the SPI-compatible (serial peripheral inter-
face) ports, the IDP (input data port), the parallel data
acquisition port (PDAP) or the UART.
Up to 65 channels of DMA are available on the processors as
shown in Table 9.
Programs can be downloaded using DMA transfers. Other
DMA features include interrupt generation upon completion of
DMA transfers, and DMA chaining for automatic linked DMA
transfers.
Delay Line DMA
The processor provides delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and therefore to external memory) with limited core
interaction.
Scatter/Gather DMA
The processor provides scatter/gather DMA functionality. This
allows processor DMA reads/writes to/from noncontiguous
memory blocks.
FFT Accelerator
The FFT accelerator implements radix-2 complex/real input,
complex output FFTs with no core intervention. The FFT accel-
erator runs at the peripheral clock frequency.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
Watchdog Timer (WDT)
The processors include a 32-bit watchdog timer that can be used
to implement a software watchdog function. A software watch-
dog can improve system reliability by forcing the processor to a
known state through generation of a system reset if the timer
expires before being reloaded by software. Software initializes
the count value of the timer, and then enables the timer.
The WDT is used to supervise the stability of the system soft-
ware. When used in this way, software reloads the WDT in a
regular manner so that the downward counting timer never
expires. An expiring timer then indicates that system software
might be out of control.
The WDT resets both the core and the internal peripherals.
Software must be able to determine if the watch dog was the
source of the hardware reset by interrogating a status bit in the
watch dog timer control register.
Table 9. DMA Channels
Peripheral
DMA Channels
SPORTs
16
PDAP
8
SPI
2
UART
2
External Port
2
Accelerators
2
Memory-to-Memory
2
MediaLB1
31
1 Automotive models only.
Table 9. DMA Channels (Continued)
Peripheral
DMA Channels
相关PDF资料 |
PDF描述 |
|---|---|
| VI-24W-CY-F4 | CONVERTER MOD DC/DC 5.5V 50W |
| REC3-2412DR/H1M/SMD | CONV DC/DC 3W 24VIN +/-12VOUT |
| VE-J5F-IZ | CONVERTER MOD DC/DC 72V 25W |
| VI-24V-CY-F3 | CONVERTER MOD DC/DC 5.8V 50W |
| MAX6518UKP095+T | IC TEMP SENSOR SW SOT23-5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21478KCPZ-1A | 功能描述:IC DSP SHARK 200MHZ 88LFCSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-1A | 功能描述:IC DSP SHARC 200MHZ LP 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-ENG | 制造商:Analog Devices 功能描述:SHARC PROCESSOR - Trays |
| ADSP-21479 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
发布紧急采购，3分钟左右您将得到回复。