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| 型号： | ADSP-2191MBSTZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144LQFP |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 主机接口，SPI，SSP，UART |
| 时钟速率： | 140MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 160kB |
| 电压 - 输入/输出： | 3.00V，3.30V |
| 电压 - 核心： | 2.50V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
| 其它名称： | ADSP-2191MBSTZ140 |
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ADSP-2191M
–20–
REV. A
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s external
signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, parameters
cannot be added meaningfully to derive longer times.
Switching characteristics specify how the processor changes its
signals. No control is possible over this timing; circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics indicate what the
processor will do in a given circumstance. Switching character-
istics can also be used to ensure that any timing requirement of
a device connected to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation.Timing requirements guarantee that the
processor operates correctly with other devices.
Clock In and Clock Out Cycle Timing
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160/80 MHz for commercial
grade and 140/70 MHz for industrial grade, when the peripheral
clock rate is one-half the core clock rate. If the peripheral clock
rate is equal to the core clock rate, the maximum peripheral clock
rate is 80 MHz for both commercial and industrial grade parts.
The peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 9. Clock In and Clock Out Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
t
CKOD
CLKOUT Delay from CLKIN
0
5.8
ns
t
CKO
CLKOUT Period
1
12.5
ns
Timing Requirements
t
CK
CLKIN Period2, 3
10
200
ns
t
CKL
CLKIN Low Pulse
4.5
ns
t
CKH
CLKIN High Pulse
4.5
ns
t
WRST
RESET Asserted Pulsewidth Low
200t
CLKOUT
ns
t
MSS
MSELx/BYPASS Stable Before
RESET Deasserted Setup
40
s
t
MSH
MSELx/BYPASS Stable After
RESET Deasserted Hold
1000
ns
t
MSD
MSELx/BYPASS Stable After
RESET Asserted
200
ns
t
PFD
Flag Output Disable Time After
RESET Asserted
10
ns
1CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
2In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t
CK = tCCLK.
3In bypass mode, t
CK = tCCLK.
Figure 8. Clock In and Clock Out Cycle Timing
tCKOD
CLKOUT
MSEL6–0
BYPASS
DF
RESET
CLKIN
tWRST
tCDD
tCK
tCKL
tMSH
tCKO
tPFD
tMSD
tMSS
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