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| 型号： | ADSP-2191MBSTZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144LQFP |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 主机接口，SPI，SSP，UART |
| 时钟速率： | 140MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 160kB |
| 电压 - 输入/输出： | 3.00V，3.30V |
| 电压 - 核心： | 2.50V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
| 其它名称： | ADSP-2191MBSTZ140 |
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–7–
REV. A
ADSP-2191M
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
The general-purpose Programmable Flag (PFx) pins can be con-
figured as outputs, can implement software interrupts, and (as
inputs) can implement hardware interrupts. Programmable Flag
pin interrupts can be configured for level-sensitive, single
edge-sensitive, or dual edge-sensitive operation.
The IRPTL register is used to force and clear interrupts. On-
chip stacks preserve the processor status and are automatically
maintained during interrupt handling. To support interrupt,
loop, and subroutine nesting, the PC stack is 33 levels deep, the
loop stack is eight levels deep, and the status stack is 16 levels
deep. To prevent stack overflow, the PC stack can generate a
stack-level interrupt if the PC stack falls below three locations full
or rises above 28 locations full.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.
DMA Controller
The ADSP-2191M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2191M’s internal memory and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capa-
ble peripherals include the Host port, SPORTs, SPI ports, and
UART. Each individual DMA-capable peripheral has a dedicated
DMA channel. To describe each DMA sequence, the DMA con-
troller uses a set of parameters—called a DMA descriptor. When
successive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one DMA
sequence auto-initiates and starts the next sequence. DMA
sequences do not contend for bus access with the DSP core;
instead DMAs “steal” cycles to access memory.
All DMA transfers use the DMA bus shown in the functional
block diagram on Page 1. Because all of the peripherals use the
same bus, arbitration for DMA bus access is needed. The arbi-
tration for DMA bus access appears in Table 4.
Host Port
The ADSP-2191M’s Host port functions as a slave on the
external bus of an external Host. The Host port interface lets a
Host read from or write to the DSP’s memory space, boot space,
or internal I/O space. Examples of Hosts include external micro-
controllers, microprocessors, or ASICs.
The Host port is a multiplexed address and data bus that provides
both an 8-bit and a 16-bit data path and operates using an asyn-
chronous transmission protocol. Through this port, an off-chip
Table 2. Peripheral Interrupts and Priority at Reset
Interrupt
ID
Reset
Priority
Slave DMA/Host Port Interface
0
SPORT0 Receive
1
SPORT0 Transmit
2
SPORT1 Receive
3
SPORT1 Transmit
4
SPORT2 Receive/SPI0
5
SPORT2 Transmit/SPI1
6
UART Receive
7
UART Transmit
8
Timer 0
9
Timer 1
10
Timer 2
11
Programmable Flag A (any PFx)
12
11
Programmable Flag B (any PFx)
13
11
Memory DMA port
14
11
Table 3. Interrupt Control (ICNTL) Register Bits
Bit
Description
0–3
Reserved
4
Interrupt Nesting Enable
5
Global Interrupt Enable
6
Reserved
7
MAC-Biased Rounding Enable
8–9
Reserved
10
PC Stack Interrupt Enable
11
Loop Stack Interrupt Enable
12–15
Reserved
Table 4. I/O Bus Arbitration Priority
DMA Bus Master
Arbitration Priority
SPORT0 Receive DMA
0—Highest
SPORT1 Receive DMA
1
SPORT2 Receive DMA
2
SPORT0 Transmit DMA
3
SPORT1 Transmit DMA
4
SPORT2 Transmit DMA
5
SPI0 Receive/Transmit DMA
6
SPI1 Receive/Transmit DMA
7
UART Receive DMA
8
UART Transmit DMA
9
Host Port DMA
10
Memory DMA
11—Lowest
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