ADSP-BF504KCPZ-3F (Analog) PDF资料下载 Datasheet(10/80 页)

您好，
买卖IC网欢迎您。
请登录
免费注册

您现在的位置：买卖IC网 > PDF目录19403 > ADSP-BF504KCPZ-3F (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 88LFCSP PDF资料下载

参数资料

型号：	ADSP-BF504KCPZ-3F
厂商：	Analog Devices Inc
文件页数：	10/80页
文件大小：	0K
描述：	IC CCD SIGNAL PROCESSOR 88LFCSP
视频文件：	Blackfin? BF50x Processor Family
标准包装：	1
系列：	Blackfin®
类型：	定点
接口：	CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
时钟速率：	300MHz
非易失内存：	闪存（16MB）
芯片上RAM：	68kB
电压 - 输入/输出：	3.30V
电压 - 核心：	1.31V
工作温度：	0°C ~ 70°C
安装类型：	表面贴装
封装/外壳：	88-VFQFN 裸露焊盘，CSP
供应商设备封装：	88-LFCSP（12x12）
包装：	托盘

Rev. A

Page 18 of 80

July 2011

ADSP-BF504/ADSP-BF504F/ADSP-BF506F

JTAG Test Access Port (TAP) on each JTAG processor. The

emulator uses the TAP to access the internal features of the pro-

cessor, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

processor must be halted to send data and commands, but once

an operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see (EE-68) Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

ADC AND ACM INTERFACE

This section describes the ADC and ACM interface. System

designers should also consult the ADSP-BF50x Blackfin Proces-

sor Hardware Reference for additional information.

The ADC control module (ACM) provides an interface that

synchronizes the controls between the processor and the inter-

nal analog-to-digital converter (ADC) module. The ACM is

available on the ADSP-BF504, ADSP-BF504F, and

ADSP-BF506F processors, and the ADC is available on the

ADSP-BF506F processor only. The analog-to-digital conver-

sions are initiated by the processor, based on external or

internal events.

The ACM allows for flexible scheduling of sampling instants

and provides precise sampling signals to the ADC.

The ACM synchronizes the ADC conversion process; generat-

ing the ADC controls, the ADC conversion start signal, and

other signals. The actual data acquisition from the ADC is done

by the SPORT peripherals.

The serial interface on the ADC allows the part to be directly

connected to the ADSP-BF504, ADSP-BF504F, and

ADSP-BF506F processors using serial interface protocols.

Figure 6 shows how to connect an external ADC to the ACM

and one of the two SPORTs on the ADSP-BF504 or

ADSP-BF504F processors.

The ADC is integrated into the ADSP-BF506F product. Figure 7

shows how to connect the internal ADC to the ACM and to one

of the two SPORTs on the ADSP-BF506F processor.

The ADSP-BF504, ADSP-BF504F, and ADSP-BF506F proces-

sors interface directly to the ADC without any glue logic

required. The availability of secondary receive registers on the

serial ports of the Blackfin processors means only one serial port

Figure 6. ADC (External), ACM, and SPORT Connections

Figure 7. ADC (Internal), ACM, and SPORT Connections

SPORTx

DRxSEC

DRxPRI

RCLKx

RFSx

ADC

(EXTERNAL)

DOUTB

DOUTA

ADSCLK

RANGE

SGL/

DIFF

A[2:0]

ACM

ACLK

ACM_RANGE

ACM_SGLDIFF

ACM_A[2:0]

ADSP-BF504 / ADSP-BF504F

SPORT

SELECT

MUX