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| 型号： | ADSP-TS101SAB1-000 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM; Package: 625 ball BGA; No of Pins: 625; Temperature Range: Ind |
| 中文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA625 |
| 封装： | 27 X 27 MM, PLASTIC, MS-034, BGA-625 |
| 文件页数： | 11/48页 |
| 文件大小： | 679K |
| 代理商： | ADSP-TS101SAB1-000 |
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ADSP-TS101S
Rev. C
|
Page 19 of 48
|
May 2009
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an approximately 100 k pull-
down for the default value. If a strap pin is not connected to an
external pull-up or logic load, the DSP samples the default value
during reset. If strap pins are connected to logic inputs, a stron-
ger external pull-down may be required to ensure default value
depending on leakage and/or low level input current of the logic
load. To set a mode other than the default mode, connect the
strap pin to a sufficiently stronger external pull-up. In a multi-
processor system, up to eight DSPs may be connected on the
cluster bus, resulting in parallel combination of strap pin pull-
down resistors. Table 16 lists and describes each of the DSP’s
strap pins.
Table 15. Pin Definitions—Power, Ground, and Reference
Signal
Type
Term
Description
VDD
Pau
VDD pins for internal logic.
VDD_A
Pau
VDD pins for analog circuits. Pay critical attention to bypassing this supply.
VDD_IO
Pau
VDD pins for I/O buffers.
VREF
I
au
Reference voltage defines the trip point for all input buffers, except RESET, IRQ3–0, DMAR3–0,
ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and TRST. The value is 1.5 V ± 100 mV (which is the TTL
trip point). VREF can be connected to a power supply or set by a voltage divider circuit. The
voltage divider should have an HF decoupling capacitor (1 nF HF SMD) connected to VSS. Tie
VSS
Gau
Ground pins.
VSS_A
G
au
Ground pins for analog circuits.
NC
No connect. Do not connect these pins to anything (not to any supply, signal, or each other),
because they are reserved and must be left unconnected.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Table 16. Pin Definitions—I/O Strap Pins
Signal
On Pin …
Description
EBOOT
BMS
EPROM boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP through the
external port or a link port
IRQEN
BM
Interrupt Enable.
0 = disable and set IRQ3–0 interrupts to level sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to edge sensitive immediately after reset
TM1
L2DIR
Test Mode 1.
0 = required setting during reset.
1 = reserved.
TM2
TMR0E
Test Mode 2.
0 = required setting during reset.
1 = reserved.
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| ADSP-TS101SAB1Z100 | 功能描述:IC DSP CTRLR 128BIT BUS 625-BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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| ADSP-TS101SAB2-050 | 制造商:Analog Devices 功能描述:TIGERSHARC - Trays |
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