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参数资料
型号： ADSP-TS101SAB1-000
厂商： ANALOG DEVICES INC
元件分类： 数字信号处理
英文描述： 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM; Package: 625 ball BGA; No of Pins: 625; Temperature Range: Ind
中文描述： 64-BIT, 125 MHz, OTHER DSP, PBGA625
封装： 27 X 27 MM, PLASTIC, MS-034, BGA-625
文件页数： 19/48页
文件大小： 679K
代理商： ADSP-TS101SAB1-000
Rev. C
|
Page 26 of 48
|
May 2009
ADSP-TS101S
1 The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive loading, see Figure 40
on Page 36.
2 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
3 CPA and DPA pins are open drains and have 0.5 k internal pull-ups.
4 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for recognition in the
current clock reference cycle.
5 This pin is a strap option. During reset, an internal resistor pulls the pin low.
6 For input specifications, see Table 21.
7 For additional requirement details, see Reset and Booting on Page 9.
8 TCK_FE indicates TCK falling edge.
9 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.
10Reference clock depends on function.
11System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31–0,
DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN, L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0,
CONTROLIMP2–0, RESET, DMAR3–0.
12System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS,
ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0, L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT,
L3DAT7–0, L3DIR, EMU.
Table 28. AC Signal Specifications (for 16.7 ns <SCLK <25 ns) (All values in this table are in nanoseconds)
Name
Description
In
p
u
tSetup
(m
in
)
In
p
u
tH
o
ld
(m
in
)
Ou
tp
u
tV
a
li
d
(m
a
x
)1
Ou
tp
u
tH
o
ld
(m
in
)
Ou
tp
u
tEn
ab
le
(m
in
)2
Ou
tpu
tDi
sab
le
(m
a
x
)2
Re
fe
re
nce
Cl
o
ck
ADDR31–0
External Address Bus
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
DATA63–0
External Data Bus
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
MSH
Memory Select Host Line
4.2
0.8
0.3
2.5
SCLK
MSSD
Memory Select SDRAM Line
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
MS1–0
Memory Select for Static Blocks
4.2
0.8
0.3
2.5
SCLK
RD
Memory Read
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
WRL
Write Low Word
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
WRH
Write High Word
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
ACK
Acknowledge for Data
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
SDCKE
SDRAM Clock Enable
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
RAS
Row Address Select
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
CAS
Column Address Select
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
SDWE
SDRAM Write Enable
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
LDQM
Low Word SDRAM Data Mask
4.2
0.8
0.3
2.5
SCLK
HDQM
High Word SDRAM Data Mask
4.2
0.8
0.3
2.5
SCLK
SDA10
SDRAM ADDR10
4.2
0.8
0.3
2.5
SCLK
HBR
Host Bus Request
2.8
0.5
SCLK
HBG
Host Bus Grant
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
BOFF
Back Off Request
2.8
0.5
SCLK
BUSLOCK
Bus Lock
4.2
0.8
0.3
2.5
SCLK
BRST
Burst Access
2.8
0.5
4.2
0.8
0.3
2.5
SCLK
BR7–0
Multiprocessing Bus Request
2.8
0.5
4.2
0.8
SCLK
FLYBY
Flyby Mode Selection
4.2
0.8
0.3
2.5
SCLK
IOEN
Flyby Mode I/O Enable
4.2
0.8
0.3
2.5
SCLK
CPA 3, 4
Core Priority Access
2.8
0.5
5.8
2.5
SCLK
DPA 3, 4
DMA Priority Access
2.8
0.5
5.8
2.5
SCLK
BMS5
Boot Memory Select
4.2
0.8
0.3
2.5
SCLK
FLAG3–0
6
FLAG Pins
4.2
1.0
4.0
SCLK
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