参数资料
型号: ADUC812BSZ
厂商: Analog Devices Inc
文件页数: 14/57页
文件大小: 0K
描述: IC ADC 12BIT MULTICH MCU 52-MQFP
产品培训模块: Process Control
标准包装: 1
系列: MicroConverter® ADuC8xx
核心处理器: 8052
芯体尺寸: 8-位
速度: 16MHz
连通性: I²C,SPI,UART/USART
外围设备: PSM,温度传感器,WDT
输入/输出数: 34
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 640 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x12b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 52-QFP
包装: 托盘
产品目录页面: 738 (CN2011-ZH PDF)
REV.
ADuC812
–21–
USER INTERFACE TO OTHER ON-CHIP ADuC812
PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC812 incorporates two 12-bit voltage output DACs
on-chip. Each has a rail-to-rail voltage output buffer capable
of driving 10 k
Ω/100 pF. Each has two selectable ranges, 0 V to
VREF (the internal band gap 2.5 V reference) and 0 V to AVDD.
Each can operate in 12-bit or 8-bit mode. Both DACs share a
control register, DACCON, and four data registers, DAC1H/L,
DAC0H/L. It should be noted that in 12-bit asynchronous mode,
the DAC voltage output will be updated as soon as the DACL
data SFR has been written; therefore, the DAC data registers
should be updated as DACH first, followed by DACL.
E
D
O
M1
G
N
R0
G
N
R1
R
L
C0
R
L
CC
N
Y
S1
D
P0
D
P
Table VIII. DACCON SFR Bit Designations
Bit
Name
Description
7
MODE
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to “1” = 8-bit mode (Write eight Bits to DACxL SFR).
Set to “0” = 12-bit mode.
6
RNG1
DAC1 Range Select Bit.
Set to “1” = DAC1 range 0–VDD.
Set to “0” = DAC1 range 0–VREF.
5
RNG0
DAC0 Range Select Bit.
Set to “1” = DAC0 range 0–VDD.
Set to “0” = DAC0 range 0–VREF.
4
CLR1
DAC1 Clear Bit.
Set to “0” = DAC1 output forced to 0 V.
Set to “1” = DAC1 output normal.
3
CLR0
DAC0 Clear Bit.
Set to “0” = DAC1 output forced to 0 V.
Set to “1” = DAC1 output normal.
2
SYNC
DAC0/1 Update Synchronization Bit.
When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can
simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both
DACs will then update simultaneously when the SYNC bit is set to “1.”
1
PD1
DAC1 Power-Down Bit.
Set to “1” = Power-on DAC1.
Set to “0” = Power-off DAC1.
0
PD0
DAC0 Power-Down Bit.
Set to “1” = Power-on DAC0.
Set to “0” = Power-off DAC0.
DACxH/L
DAC Data Registers
Function
DAC data registers, written by user to update the DAC output.
SFR Address
DAC0L (DAC0 Data Low Byte)
F9H; DAC1L (DAC1 data low byte)FBH
DAC0H (DAC0 Data High Byte)
FAH; DAC1H(DAC1 data high byte)FCH
Power-On Default Value
00H
All four registers
Bit Addressable
No
All four registers
The 12-bit DAC data should be written into DACxH/L, right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
DAC Control
DACCON
Register
SFR Address
FDH
Power-On Default Value
04H
Bit Addressable
No
F
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