参数资料
型号: ADUC812BSZ
厂商: Analog Devices Inc
文件页数: 33/57页
文件大小: 0K
描述: IC ADC 12BIT MULTICH MCU 52-MQFP
产品培训模块: Process Control
标准包装: 1
系列: MicroConverter® ADuC8xx
核心处理器: 8052
芯体尺寸: 8-位
速度: 16MHz
连通性: I²C,SPI,UART/USART
外围设备: PSM,温度传感器,WDT
输入/输出数: 34
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 640 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x12b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 52-QFP
包装: 托盘
产品目录页面: 738 (CN2011-ZH PDF)
REV.
ADuC812
–39–
Secondary Interrupt
IE2
Enable Register
SFR Address
A9H
Power-On Default Value
00H
Bit Addressable
No
———
I
M
S
P
EI
S
E
Table XXIV. IE2 SFR Bit Designations
Bit
Name
Description
7
Reserved for future use.
6
Reserved for future use.
5
Reserved for future use.
4
Reserved for future use.
3
Reserved for future use.
2
Reserved for future use.
1
EPSMI
Written by user to Enable “1” or Disable “0” power supply monitor interrupt.
0
ESI
Written by user to Enable “1” or Disable “0” I
2C/SPI serial port interrupt.
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt.
An interrupt of high priority may interrupt the service routine of
a low priority interrupt. If two interrupts of different priorities
occur at the same time, the higher level interrupt will be served
first. An interrupt cannot be interrupted by another interrupt of
the same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed, as shown
in Table XXV.
Table XXV. Priority within an Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt
IE0
2
External Interrupt 0
ADCI
3
ADC Interrupt
TF0
4
Timer/Counter 0 Interrupt
IE1
5
External Interrupt 1
TF1
6
Timer/Counter 1 Interrupt
I2CI + ISPI
7
I
2C/SPI Interrupt
RI + TI
8
Serial Interrupt
TF2 + EXF2
9 (Lowest)
Timer/Counter 2 Interrupt
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in the Table XXVI.
Table XXVI. Interrupt Vector Addresses
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
ADCI
0033H
I2CI + ISPI
003BH
PSMI
0043H
F
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