参数资料
型号: ADUC812BSZ
厂商: Analog Devices Inc
文件页数: 56/57页
文件大小: 0K
描述: IC ADC 12BIT MULTICH MCU 52-MQFP
产品培训模块: Process Control
标准包装: 1
系列: MicroConverter® ADuC8xx
核心处理器: 8052
芯体尺寸: 8-位
速度: 16MHz
连通性: I²C,SPI,UART/USART
外围设备: PSM,温度传感器,WDT
输入/输出数: 34
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 640 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x12b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 52-QFP
包装: 托盘
产品目录页面: 738 (CN2011-ZH PDF)
REV.
ADuC812
–8–
Mnemonic
Type
Function
PSEN
O
Program Store Enable, Logic Output. This output is a control signal that enables the external program
memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution.
PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit
address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.
EA
I
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from
internal program memory locations 0000H to 1FFFH. When held low, this input enables the device to fetch
all instructions from external program memory.
P0.7–P0.0
I/O
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in
(A0–A7)
that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data
bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups
when emitting 1s.
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.
Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fun-
damental. Noise is the rms sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent upon the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error.
Voltage Output Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.
PIN FUNCTION DESCRIPTIONS (continued)
F
EP
Exposed Pad. For the LFCSP, the exposed pad must be soldered and left unconnected.
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