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参数资料
| 型号： | ADUC836BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 16BIT W/MCU 52-MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 7x16b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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ADuC836
–42–
ADuC836
–43–
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
or interrupt within a reasonable amount of time if the ADuC836
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI.The watchdog function can be disabled
by clearing the WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR.When enabled, the watchdog circuit will
generate a system reset or interrupt (WDS) if the user program
fails to set the watchdog (WDE) bit within a predetermined
amount of time (see PRE3–0 bits in WDCON).The watchdog
timer itself is a 16-bit counter that is clocked at 32.768 kHz.The
watchdog timeout interval can be adjusted via the PRE3–0 bits in
WDCON. Full control and status of the watchdog timer function
can be controlled via theWatchdogTimer Control SFR (WDCON).
The WDCON SFR can only be written by user software if the
double write sequence described in WDWR below is initiated on
every write access to the WDCON SFR.
Table XIX. WDCON SFR Bit Designations
Bit
Name
Description
7
PRE3
Watchdog Timer Prescale Bits.
6
PRE2
The Watchdog timeout period is given by the equation tWD = (2PRE (29/fPLL))
5
PRE1
(0 PRE 7; fPLL = 32.768 kHz)
4
PRE0
Timeout
PRE3 PRE2
PRE1
PRE0
Period (ms)
Action
0
15.6
Reset or Interrupt
0
1
31.2
Reset or Interrupt
0
1
0
62.5
Reset or Interrupt
0
1
125
Reset or Interrupt
0
1
0
250
Reset or Interrupt
0
1
0
1
500
Reset or Interrupt
0
1
0
1000
Reset or Interrupt
0
1
2000
Reset or Interrupt
1
0
0.0
Immediate Reset
PRE3–0 > 1001
Reserved
3
WDIR
Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt
response instead of a system reset when the watchdog timeout period has expired.This interrupt is not disabled by
the CLR EA instruction, and it is also a fixed, high priority interrupt. If the watchdog is not being used to monitor
the system, it can alternatively be used as a timer.The prescaler is used to set the timeout period in which an
interrupt will be generated. (See also Note 1,Table XXXIX in the Interrupt System section.)
2
WDS
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
1
WDE
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the watchdog timeout
period, the watchdog will generate a reset or interrupt, depending on WDIR.
Cleared under the following conditions: User writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt.
0
WDWR
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence.The WDWR bit must be set and the
very next instruction must be a write instruction to the WDCON SFR. For example:
CLR
EA
; disable interrupts while writing
; to WDT
SETB
WDWR
; allow write to WDCON
MOV
WDCON, #72h
; enable WDT for 2.0s timeout
SETB
EA
; enable interrupts again (if rqd)
WDCON
Watchdog Timer Control Register
SFR Address
C0H
Power-On Default Value
10H
Bit Addressable
Yes
REV. A
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