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参数资料
| 型号： | ADUC836BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 61/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 16BIT W/MCU 52-MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 7x16b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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ADuC836
–64–
ADuC836
–65–
Power Supplies
The ADuC836’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or +5% of the
nominal 5 V level, the chip will function equally well at any power
supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AVDD and DVDD,
respectively) allow AVDD to be kept relatively free of noisy digital
signals that are often present on the system DVDD line. In this mode,
the part can also operate with split supplies, that is, using different
voltage supply levels for each supply. For example, this means that
the system can be designed to operate with a DVDD voltage level of
3 V while the AVDD level can be at 5V, or vice-versa if required. A
typical split-supply configuration is shown in Figure 61.
DVDD
48
34
20
ADuC836
5
6
AGND
AVDD
–+
0.1F
10F
ANALOG SUPPLY
10F
DGND
35
21
47
0.1F
DIGITAL SUPPLY
–+
Figure 61. External Dual-Supply Connections
As an alternative to providing two separate power supplies, AVDD
can be kept quiet by placing a small series resistor and/or ferrite
bead between it and DVDD, and then decoupling AVDD separately
to ground. An example of this configuration is shown in Figure 62.
In this configuration, other analog circuitry (such as op amps,
voltage reference, and so on) can be powered from the AVDD
supply line as well.
DVDD
48
34
20
ADuC836
5
6
AGND
AVDD
0.1F
10F
DGND
35
21
47
0.1F
–
+
DIGITAL SUPPLY
10F
1.6
BEAD
Figure 62. External Single-Supply Connections
Notice that in Figures 61 and 62, a large value (10 F) reservoir
capacitor sits on DVDD and a separate 10 F capacitor sits on
AVDD. Also, local decoupling capacitors (0.1 F) are located at
each VDD pin of the chip. As per standard design practice, be sure
to include all of these capacitors and ensure the smaller capacitors
are closest to each VDD pin with lead lengths as short as possible.
Connect the ground terminal of each of these capacitors directly to
the underlying ground plane. Finally, it should also be noticed that,
at all times, the analog and digital ground pins on the ADuC836
should be referenced to the same system ground reference point.
Power-On Reset (POR) Operation
An internal POR (Power-On Reset) is implemented on the
ADuC836. For DVDD below 2.45 V, the internal POR will hold
the ADuC836 in reset. As DVDD rises above 2.45 V, an internal
timer will time out for typically 128 ms before the part is
released from reset.The user must ensure that the power supply
has reached a stable 2.7 V minimum level by this time. Likewise
on power-down, the internal POR will hold the ADuC836 in
reset until the power supply has dropped below 1 V. Figure 63
illustrates the operation of the internal POR in detail.
128ms TYP
1.0V TYP
128ms TYP
2.45V TYP
1.0V TYP
INTERNAL
CORE RESET
DVDD
Figure 63. Internal Power-on-Reset Operation
Power Consumption
The DVDD power supply current consumption is specified in
normal, idle, and power-down modes.The AVDD power supply
current is specified with the analog peripherals disabled.The
normal mode power consumption represents the current drawn
from DVDD by the digital core.The other on-chip peripherals
(watchdog timer, power supply monitor, and so on) consume
negligible current and are therefore lumped in with the normal
operating current here. Of course, the user must add any currents
sourced by the parallel and serial I/O pins, and those sourced
by the DAC in order to determine the total current needed at the
ADuC836’s DVDD and AVDD supply pins. Also, current drawn
from the DVDD supply will increase by approximately 5 mA during
Flash/EE erase and program cycles.
REV. A
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