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参数资料
| 型号： | ADUC836BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 16BIT W/MCU 52-MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 7x16b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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ADuC836
–44–
ADuC836
–45–
SERIAL PERIPHERAL INTERFACE
The ADuC836 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full-
duplex. It should be noted that the SPI pins SCLOCK and MOSI
are multiplexed with the I2C pins SCLOCK and SDATA.The pins
are controlled via the I2CCON SFR only if SPE is clear. SPI can
be configured for master or slave operation and typically consists of
four pins:
SCLOCK (Serial Clock I/O Pin), Pin 26
The master clock (SCLOCK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period.Therefore, a byte is transmitted/received after
eight SCLOCK periods.The SCLOCK pin is configured as an
output in master mode and as an input in Slave mode. In Master
mode, the bit rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XXI). In Slave mode, the SPICON register will have
to be configured with the phase and polarity (CPHA and CPOL)
as the master, as for both Master and Slave modes the data is
transmitted on one edge of the SCLOCK signal and sampled on
the other.
MISO (Master In, Slave Out Data I/O Pin), Pin 14
The MISO (master in slave out) pin is configured as an input line
in Master mode and an output line in Slave mode.The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out).The data is transferred as byte-
wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin 27
The MOSI (master out slave in) pin is configured as an output
line in Master mode and an input line in Slave mode.The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in).The data is transferred as byte-
wide (8-bit) serial data, MSB first.
SS (Slave Select Input Pin), Pin 13
The Slave Select (SS) input pin is only used when the ADuC836
is configured in SPI Slave mode.This line is active low. Data is
only received or transmitted in Slave mode when the SS pin is low,
allowing the ADuC836 to be used in single master, multislave SPI
configurations. If CPHA = 1, the SS input may be permanently
pulled low.With CPHA = 0, the SS input must be driven low
before the first bit in a byte wide transmission or reception and
return high again after the last bit in that byte-wide transmission or
reception. In SPI Slave mode, the logic level on the external SS pin
(Pin 13) can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
Table XXI. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6
WCOL
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I2C interface.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by user to enable Master mode operation (SCLOCK is an output).
Cleared by user to enable Slave mode operation (SCLOCK is an input).
3
CPOL*
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
2
CPHA*
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
1
SPR1
SPI Bit Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bitrate) in Master mode as follows:
SPR1
SPR0
Selected Bit Rate
0
fCORE/2
0
1
fCORE/4
1
0
fCORE/8
1
fCORE/16
In SPI Slave mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit.
*The CPOL and CPHA bits should both contain the same values for master and slave devices.
REV. A
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