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参数资料
| 型号： | ADUC836BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 59/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 16BIT W/MCU 52-MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 7x16b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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ADuC836
–62–
ADuC836
–63–
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each inter-
rupt. An interrupt of a high priority may interrupt the service
routine of a low priority interrupt, and if two interrupts of differ-
ent priority occur at the same time, the higher level interrupt will
be serviced first. An interrupt cannot be interrupted by another
interrupt of the same priority level. If two interrupts of the same
priority level occur simultaneously, a polling sequence is used to
determine which interrupt is serviced first.The polling sequence
is shown in Table XXXVIII.
Table XXXVIII. Priority within an Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt
WDS
2
Watchdog Interrupt
IE0
3
External Interrupt 0
RDY0/RDY1
4
ADC Interrupt
TF0
5
Timer/Counter 0 Interrupt
IE1
6
External Interrupt 1
TF1
7
Timer/Counter 1 Interrupt
ISPI/I2CI
8
SPI Interrupt
RI + TI
9
Serial Interrupt
TF2 + EXF2
10
Timer/Counter 2 Interrupt
TII
11 (Lowest)
Time Interval Counter Interrupt
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is loaded
into the program counter.The interrupt vector addresses are
shown in Table XXXIX.
Table XXXIX. Interrupt Vector Addresses
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
RDY0/RDY1 (ADC)
0033H
ISPI/I2CI
003BH
PSMI
0043H
TII
0053H
WDS (WDIR = 1)*
005BH
*The watchdog can be configured to generate an interrupt instead of
a reset when it times out.This is used for logging errors or examining
the internal status of the microcontroller core to understand, from
a software debug point of view, why a watchdog timeout occurred.
The watchdog interrupt is slightly different from the normal inter-
rupts in that its priority level is always set to 1 and it is not possible
to disable the interrupt via the global disable bit (EA) in the IE SFR.
This is done to ensure that the interrupt will always be responded
to if a watchdog timeout occurs.The watchdog will only produce an
interrupt if the watchdog timeout is greater than zero.
REV. A
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