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| 型号： | ADUC836BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 49/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 16BIT W/MCU 52-MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 7x16b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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ADuC836
–52–
ADuC836
–53–
TCON
Timer/Counter 0 and 1 Control Register
SFR Address
88H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXVII. TCON SFR Bit Designations
Bit
Name
Description
7
TF1
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
6
TR1
Timer 1 Run Control Bit.
Set by user to turn on Timer/Counter 1.
Cleared by user to turn off Timer/Counter 1.
5
TF0
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
4
TR0
Timer 0 Run Control Bit.
Set by user to turn on Timer/Counter 0.
Cleared by user to turn off Timer/Counter 0.
3
IE1*
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source rather than the on-chip hardware, controls the request flag.
2
IT1*
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
1
IE0*
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware.
0
IT0*
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
*These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Both Timer 0 and Timer 1 consist of two 8-bit registers.These can be used as independent registers or combined to be a single 16-bit
register, depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH, 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH, respectively.
REV. A
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