参数资料
| 型号： | ADV7180WBCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 81/116页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO DECODER SDTV 40LFCSP |
| 标准包装： | 1 |
| 类型： | 视频解码器 |
| 应用： | 数码相机，手机，便携式视频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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Data Sheet
ADV7180
Rev. I | Page 67 of 116
VPS/PDC/UTC/GEMSTAR
The readback registers for VPS, PDC, and UTC are shared.
Gemstar is a high data rate standard and is available only through
the ancillary stream. However, for evaluation purposes, any one
line of Gemstar is available through the I2C registers sharing the
same register space as PDC, UTC, and VPS. Therefore, only VPS,
PDC, UTC, or Gemstar can be read through the I2C at one time.
To identify the data that should be made available in the I2C
registers, the user must program I2C_GS_VPS_PDC_UTC[1:0]
(Register Address 0x9C, user sub map).
I2C_GS_VPS_PDC_UTC[1:0] (VDP), Address 0x9C[7:6],
User Sub Map
Specifies which standard result is available for I2C readback.
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear,
Address 0x78[4], User Sub Map, Write Only, Self-Clearing
Setting GS_PDC_VPS_UTC_CLEAR to 1 reinitializes the
GS/PDC/VPS/UTC data readback registers.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available,
Address 0x78[4], User Sub Map, Read Only
When GS_PDC_VPS_UTC_AVL is 0, no GS, PDC, VPS, or
UTC data is detected.
When GS_PDC_VPS_UTC_AVL is 1, one GS, PDC, VPS, or
UTC data is detected.
VDP_GS_VPS_PDC_UTC, Readback Registers,
Address 0x84 to Address 0x90
See Table 85 for information on the readback registers.
VPS
The VPS data bits are biphase decoded by the VDP. The decoded
data is available in both the ancillary stream and in the I2C
readback registers. VPS decoded data is available in the
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers (Address 0x84 to Address 0x90, user sub map). The
GS_PDC_VPS_UTC_AVL bit is set if the user programmed
Gemstar
The Gemstar-decoded data is made available in the ancillary
stream, and any one line of Gemstar is also available in the I2C
registers for evaluation purposes. To read Gemstar results
through the I2C registers, the user must program
Table 84. I2C_GS_VPS_PDC_UTC[1:0] Function
I2C_GS_VPS_PDC_UTC[1:0]
Description
00 (default)
Gemstar 1×/2×
01
VPS
10
PDC
11
UTC
VDP supports autodetection of the Gemstar standard, either
Gemstar 1× or Gemstar 2×, and decodes accordingly. For the
autodetection mode to work, the user must set the AUTO_
DETECT_GS_TYPE bit (Register 0x61, user sub map) and
program the decoder to decode Gemstar 2× on the required lines
through line programming. The type of Gemstar decoded can
be determined by observing the GS_DATA_TYPE bit
(Register 0x78, user sub map).
AUTO_DETECT_GS_TYPE, Address 0x61[4], User Sub Map
Setting AUTO_DETECT_GS_TYPE to 0 (default) disables the
autodetection of the Gemstar type.
Setting AUTO_DETECT_GS_TYPE to 1 enables the
autodetection of the Gemstar type.
GS_DATA_TYPE, Address 0x78[5], User Sub Map, Read Only
Identifies the decoded Gemstar data type.
When GS_DATA_TYPE is 0, Gemstar 1× mode is detected.
Read two data bytes from Register 0x84.
When GS_DATA_TYPE is 1, Gemstar 2× mode is detected.
Read four data bytes from Register 0x84.
The Gemstar data that is available in the I2C register can be
from any line of the input video on which Gemstar was decoded.
To read the Gemstar data on a particular video line, the user
should use the manual configuration described in Table 70 and
Table 71 and enable Gemstar decoding only on the required line.
PDC/UTC
PDC and UTC are data transmitted through Teletext Packet 8/30
Format 2 (Magazine 8, Row 30, Design Code 2 or Design Code 3)
and Packet 8/30 Format 1 (Magazine 8, Row 30, Design Code 0
or Design Code 1). Therefore, if PDC or UTC data is to be read
through I2C, the corresponding teletext standard (WST or PAL
System B) should be decoded by VDP. The whole teletext
decoded packet is output on the ancillary data stream. The user
can look for the magazine number, row number, and design
code and qualify the data as PDC, UTC, or neither of these.
If PDC/UTC packets are identified, Byte 0 to Byte 12 are updated
to the VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
registers, and the GS_PDC_VPS_UTC_AVL bit is set. The full
packet data is also available in the ancillary data format.
Note that the data available in the I2C register depends on the
status of the WST_PKT_DECODE_DISABLE bit (Bit 3,
Subaddress 0x60, user sub map).
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相关代理商/技术参数 |
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| ADV7180WBCPZ-REEL | 功能描述:IC VIDEO DECODER SDTV 40LFCSP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| ADV7180WBST48Z | 制造商:Analog Devices 功能描述: |
| ADV7180WBST48Z-RL | 功能描述:视频 IC 10-bit 4x Oversampling SDTV Decoder RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| ADV7180WBSTZ | 功能描述:视频 IC 10-bit 4x Oversampling SDTV Decoder RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| ADV7180WBSTZ-REEL | 功能描述:视频 IC 10-bit 4x Oversampling SDTV Decoder RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
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