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参数资料
型号： AGLN010V5-UC36
元件分类： FPGA
英文描述： FPGA, 260 CLBS, 10000 GATES, 250 MHz, PBGA36
封装： 4 X 4 MM, 0.8 MM HEIGHT, 0.4 MM PITCH, UC-36
文件页数： 49/140页
文件大小： 4325K
代理商： AGLN010V5-UC36
IGLOO nano DC and Switching Characteristics
2- 2
R ev isio n 1 0
Table 2-2 Recommended Operating Conditions 1
Symbol
Parameter
Extended
Commercial
Industrial
Units
TA
Ambient temperature
–20 to +70 2
–40 to +85 2
°C
TJ
Junction temperature
–20 to + 85 2
–40 to +100 2
°C
VCC
1.5 V DC core supply voltage3
1.425 to 1.575
V
1.2 V–1.5 V wide range core voltage4,5
1.14 to 1.575
V
VJTAG
JTAG DC voltage
1.4 to 3.6
V
VPUMP 6 Programming voltage
Programming mode
3.15 to 3.45
V
Operation
0 to 3.6
V
VCCPLL7 Analog power supply
(PLL)
1.5 V DC core supply voltage3
1.425 to 1.575
V
1.2 V–1.5 V wide range core
supply voltage4
1.14 to 1.575
V
VCCI and
VMV 8,9
1.2 V DC supply voltage 4
1.14 to 1.26
V
1.2 V DC wide range supply voltage 4
1.14 to 1.575
V
1.5 V DC supply voltage
1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
V
3.3 V DC wide range supply voltage 10
2.7 to 3.6
V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends
that the user follow best design practices using Actel’s timing and power simulation tools.
3. For IGLOO nano V5 devices
4. For IGLOO nano V2 devices only, operating at VCCI ≥ VCC
5. IGLOO nano V5 devices can be programmed with the VCC core voltage at 1.5 V only. IGLOO nano V2 devices can be
programmed with the VCC core voltage at 1.2 V (with FlashPro4 only) or 1.5 V. If you are using FlashPro3 and want to
do in-system programming using 1.2 V, please contact the factory.
6. VPUMP can be left floating during operation (not programming mode).
7. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information.
8. VMV pins must be connected to the corresponding VCCI pins. See the Pin Descriptions chapter of the IGLOO nano
FPGA Fabric User’s Guide for further information.
9. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank.
10. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
Table 2-3 Flash Programming Limits – Retention, Storage, and Operating Temperature1
Product
Grade
Programming
Cycles
Program Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG (°C)
2
Maximum Operating Junction
Temperature TJ (°C)
2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
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