参数资料
型号: AT32UC3L032-D3HT
厂商: Atmel
文件页数: 11/174页
文件大小: 0K
描述: MCU AVR32 32K FLASH 48TTLGA
产品培训模块: AVR® UC3 Introduction
标准包装: 2,450
系列: AVR®32 UC3 L
核心处理器: AVR
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
数据转换器: A/D 9x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-UFLGA
包装: 托盘
108
32099I–01/2012
AT32UC3L016/32/64
9.5.4.1
Operation example
Figure 9-2 shows a typical memory map, consisting of some memories, some simple peripher-
als, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has
been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has no
way of accessing for example the Transmit Holding register in the UART, present on address X
on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs can be
accessed. If for example RTR0 is configured to point to address X, an access to RTR0 will be
remapped by the SAU to address X according to the algorithm presented above. By program-
ming the SAU RTRs, specific addresses in modules that have generally been protected by the
MPU can be performed.
Figure 9-2.
Example Memory Map for a System with SAU
9.5.5
Interrupts
The SAU can generate an interrupt request to signal different events. All events that can gener-
ate an interrupt request have dedicated bits in the Status Register (SR). An interrupt request will
be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are
set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared
by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt
request remains active until the corresponding bit in SR is cleared by writing a one to the corre-
sponding bit in the Interrupt Clear Register (ICR).
The following SR bits are used for signalling the result of SAU accesses:
RTR Address Error (RTRADR) is set if an illegal address is written to the RTRs. Only
addresses in the range 0xFFFC0000-0xFFFFFFFF are allowed.
Master Interface Bus Error (MBERROR) is set if any of the conditions listed in Section 9.5.7
occurred.
Transmit Holding
Baudrate
Control
Receive Holding
Channel 1
RTR0
RTR1
Address X
Address Z
UART
SAU
CONFIG
SAU
CHANNEL
UR
RTR62
..
.
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