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参数资料
型号： AT32UC3L032-D3HT
厂商： Atmel
文件页数： 152/174页
文件大小： 0K
描述： MCU AVR32 32K FLASH 48TTLGA
产品培训模块： AVR® UC3 Introduction
标准包装： 2,450
系列： AVR®32 UC3 L
核心处理器： AVR
芯体尺寸： 32-位
速度： 50MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，DMA，POR，PWM，WDT
输入/输出数： 36
程序存储器容量： 32KB（32K x 8）
程序存储器类型： 闪存
RAM 容量： 16K x 8
电压 - 电源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
数据转换器： A/D 9x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 48-UFLGA
包装： 托盘
79
32099I–01/2012
AT32UC3L016/32/64
also the other word in the same 64-bit location is read. The first word is output on the bus, and
the other word is put into an internal buffer. If a read to a sequential address is to be performed
in the next cycle, the buffered word is output on the bus, while the next 64-bit location is read
from the flash memory. Thus, latency in 1 wait state mode is hidden for sequential fetches.
The programmer can select the wait states required by writing to the FWS field in the Flash Con-
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash memory.
In 0ws mode, no wait states are encountered on any flash read operations. In 1 ws mode, one
stall cycle is encountered on the first access in a single or burst transfer. In 1 ws mode, if the first
access in a burst access is to an address that is not 64-bit aligned, an additional stall cycle is
also encountered when reading the second word in the burst. All subsequent words in the burst
are accessed without any stall cycles.
The Flash Controller provides two sets of buffers that can be enabled in order to speed up
instruction fetching. These buffers can be enabled by writing a one to the FCR.SEQBUF and
FCR.BRBUF bits. The SEQBUF bit enables buffering hardware optimizing sequential instruction
fetches. The BRBUF bit enables buffering hardware optimizing tight inner loops. These buffers
are never used when the flash is in 0 wait state mode. Usually, both these buffers should be
enabled when operating in 1 wait state mode. Some users requiring absolute cycle determinism
may want to keep the buffers disabled.
The Flash Controller address space is displayed in Figure 8-1. The memory space between
address pw and the User page is reserved, and reading addresses in this space returns an
undefined result. The User page is permanently mapped to an offset of 0x00800000 from the
start address of the flash memory.
Table 8-1.
User Page Addresses
Memory type
Start address, byte sized
Size
Main array
0
pw bytes
User
0x00800000
w bytes
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