参数资料
型号: AT32UC3L032-D3HT
厂商: Atmel
文件页数: 33/174页
文件大小: 0K
描述: MCU AVR32 32K FLASH 48TTLGA
产品培训模块: AVR® UC3 Introduction
标准包装: 2,450
系列: AVR®32 UC3 L
核心处理器: AVR
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
数据转换器: A/D 9x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-UFLGA
包装: 托盘
dsPIC30F6011/6012/6013/6014
DS70117F-page 194
2006 Microchip Technology Inc.
TABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C
≤ TA ≤ +85°C for Industrial
-40°C
≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CS10
TcSCKL
CSCK Input Low Time
(CSCK pin is an input)
TCY/2 + 20
ns
CSCK Output Low Time(3)
(CSCK pin is an output)
30
ns
CS11
TcSCKH
CSCK Input High Time
(CSCK pin is an input)
TCY/2 + 20
ns
CSCK Output High Time(3)
(CSCK pin is an output)
30
ns
CS20
TcSCKF
CSCK Output Fall Time(4)
(CSCK pin is an output)
—10
25
ns
CS21
TcSCKR
CSCK Output Rise Time(4)
(CSCK pin is an output)
—10
25
ns
CS30
TcSDOF
CSDO Data Output Fall Time(4)
—10
25
ns
CS31
TcSDOR
CSDO Data Output Rise Time(4)
—10
25
ns
CS35
TDV
Clock edge to CSDO data valid
10
ns
CS36
TDIV
Clock edge to CSDO tri-stated
10
20
ns
CS40
TCSDI
Setup time of CSDI data input to
CSCK edge (CSCK pin is input
or output)
20
ns
CS41
THCSDI
Hold time of CSDI data input to
CSCK edge (CSCK pin is input
or output)
20
ns
CS50
TcoFSF(1)
COFS Fall Time
(COFS pin is output)
—10
25
ns
CS51
TcoFSR(1)
COFS Rise Time
(COFS pin is output)
—10
25
ns
CS55
TscoFS
Setup time of COFS data input to
CSCK edge (COFS pin is input)
20
ns
CS56
THCOFS
Hold time of COFS data input to
CSCK edge (COFS pin is input)
20
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
2:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3:
The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4:
Assumes 50 pF load on all DCI pins.
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