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参数资料
型号： AT32UC3L032-D3HT
厂商： Atmel
文件页数： 150/174页
文件大小： 0K
描述： MCU AVR32 32K FLASH 48TTLGA
产品培训模块： AVR® UC3 Introduction
标准包装： 2,450
系列： AVR®32 UC3 L
核心处理器： AVR
芯体尺寸： 32-位
速度： 50MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，DMA，POR，PWM，WDT
输入/输出数： 36
程序存储器容量： 32KB（32K x 8）
程序存储器类型： 闪存
RAM 容量： 16K x 8
电压 - 电源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
数据转换器： A/D 9x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 48-UFLGA
包装： 托盘
77
32099I–01/2012
AT32UC3L016/32/64
8.
Flash Controller (FLASHCDW)
Rev: 1.0.2.0
8.1
Features
Controls on-chip flash memory
Supports 0 and 1 wait state bus access
Buffers reducing penalty of wait state in sequential code or loops
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle for sequential reads
Secure State for supporting FlashVault technology
32-bit HSB interface for reads from flash and writes to page buffer
32-bit PB interface for issuing commands to and configuration of the controller
Flash memory is divided into 16 regions can be individually protected or unprotected
Additional protection of the Boot Loader pages
Supports reads and writes of general-purpose Non Volatile Memory (NVM) bits
Supports reads and writes of additional NVM pages
Supports device protection through a security bit
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit
8.2
Overview
The Flash Controller (FLASHCDW) interfaces the on-chip flash memory with the 32-bit internal
HSB bus. The controller manages the reading, writing, erasing, locking, and unlocking
sequences.
8.3
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
8.3.1
Power Management
If the CPU enters a sleep mode that disables clocks used by the FLASHCDW, the FLASHCDW
will stop functioning and resume operation after the system wakes up from sleep mode.
8.3.2
Clocks
The FLASH CDW has two bus clocks co nn ect e d: O n e High Spe e d Bu s cl ock
(CLK_FLASHCDW_HSB) and one Peripheral Bus clock (CLK_FLASHCDW_PB). These clocks
are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by
writing to the Power Manager. The user has to ensure that CLK_FLASHCDW_HSB is not turned
off before reading the flash or writing the pagebuffer and that CLK_FLASHCDW_PB is not
turned off before accessing the FLASHCDW configuration and control registers. Failing to do so
may deadlock the bus.
8.3.3
Interrupts
The FLASHCDW interrupt request lines are connected to the interrupt controller. Using the
FLASHCDW interrupts requires the interrupt controller to be programmed first.
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