参数资料
型号: AT32UC3L032-D3HT
厂商: Atmel
文件页数: 77/174页
文件大小: 0K
描述: MCU AVR32 32K FLASH 48TTLGA
产品培训模块: AVR® UC3 Introduction
标准包装: 2,450
系列: AVR®32 UC3 L
核心处理器: AVR
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
数据转换器: A/D 9x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-UFLGA
包装: 托盘
3
32099I–01/2012
AT32UC3L016/32/64
1.
Description
The Atmel AVR AT32UC3L016/32/64 is a complete system-on-chip microcontroller based on
the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-per-
formance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications,
with particular emphasis on low power consumption, high code density, and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is
used together with the MPU to provide the required security and integrity.
Higher computation capability is achieved using a rich set of DSP instructions.
The AT32UC3L016/32/64 embeds state-of-the-art picoPower technology for ultra-low power
consumption. Combined power control techniques are used to bring active current consumption
down to 165A/MHz, and leakage down to 9nA while still retaining a bank of backup registers.
The device allows a wide range of trade-offs between functionality and power consumption, giv-
ing the user the ability to reach the lowest possible power consumption with the feature set
required for the application.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The AT32UC3L016/32/64 incorporates on-chip Flash and SRAM memories for secure and fast
access. The FlashVault technology allows secure libraries to be programmed into the device.
The secure libraries can be executed while the CPU is in Secure State, but not read by non-
secure software in the device. The device can thus be shipped to end customers, who will be
able to program their own code into the device to access the secure libraries, but without risk of
compromising the proprietary secure code.
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked.
The Peripheral Event System allows peripherals to receive, react to, and send peripheral events
without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low
power sleep modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-on Reset (POR), Brown-out Detector (BOD), and Supply Monitor (SM). The
device features several oscillators, such as Digital Frequency Locked Loop (DFLL), Oscillator 0
(OSC0), and system RC oscillator (RCSYS). Either of these oscillators can be used as source
for the system clock. The DFLL is a programmable internal oscillator from 40 to 150MHz. It can
be tuned to a high accuracy if an accurate refernce clock is running, e.g. the 32 KHz crystal
oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter mode or calendar mode.
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