参数资料
型号: AT32UC3L032-D3HT
厂商: Atmel
文件页数: 25/174页
文件大小: 0K
描述: MCU AVR32 32K FLASH 48TTLGA
产品培训模块: AVR® UC3 Introduction
标准包装: 2,450
系列: AVR®32 UC3 L
核心处理器: AVR
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
数据转换器: A/D 9x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-UFLGA
包装: 托盘
16
32099I–01/2012
AT32UC3L016/32/64
3.4
I/O Line Considerations
3.4.1
JTAG Pins
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled dur-
ing reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG
pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled.
Please refer to Section 3.2.3 on page 11 for the JTAG port connections.
3.4.2
PA00
Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the
application.
3.4.3
RESET_N Pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by external circuitry.
3.4.4
TWI Pins PA21/PB04/PB05
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the same characteristics as other GPIO pins. Selected pins are also SMBus compliant (refer to
Section 3.2 on page 9). As required by the SMBus specification, these pins provide no leakage
path to ground when the AT32UC3L016/32/64 is powered down. This allows other devices on
the SMBus to continue communicating even though the AT32UC3L016/32/64 is not powered.
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the
GPIO Module Configuration chapter for details.
3.4.5
TWI Pins PA05/PA07/PA17
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the same characteristics as other GPIO pins.
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the
GPIO Module Configuration chapter for details.
3.4.6
GPIO Pins
All the I/O lines integrate a pull-up resistor
. Programming of this pull-up resistor is performed
independently for each I/O line through the GPIO Controller. After reset, I/O lines default as
inputs with pull-up resistors disabled, except PA00. PA20 selects SCIF-RC32OUT (GPIO Func-
tion F) as default enabled after reset.
3.4.7
High-Drive Pins
The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to
Section 32. on page 770 for electrical characteristics.
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