参数资料
型号: AT85C51SND3B1-7FTUL
厂商: Atmel
文件页数: 14/119页
文件大小: 0K
描述: IC DECODER/ENCODER DGTL 100CBGA
标准包装: 90
类型: 音频编码器/解码器
应用: 移动电话,手机,视频显示器
电压 - 电源,数字: 1.65 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 100-TFBGA
供应商设备封装: 100-CTBGA(9x9)
包装: 托盘
110
AT85C51SND3B
7632D–MP3–01/07
writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the
data. If the IN Endpoint is composed of multiple banks, this also switches to the next
data bank. The TXINI and FIFOCON bits are automatically updated by hardware
regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware
can write data to the bank, and cleared by hardware when the bank is full.
“Autoswitch” Mode
In this mode, the clear of the FIFOCON bit is performed automatically by hardware each
time the Endpoint bank is full. The firmware has to check if the next bank is empty or not
before writing the next data. On TXINI interrupt, the firmware fills a complete bank. A
new interrupt will be generated each time the current bank becomes free.
Detailed Description
Standard Mode without
AUTOSW
In this mode (AUTOSW cleared), the data are written by the CPU, following the next
flow:
When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled
(TXINE set) and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending
the software architecture choice,
The CPU acknowledges the interrupt by clearing TXINI,
The CPU can write the data into the current bank (write in UEDATX),
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
HW
Example with 1 IN data bank
write data from CPU
BANK 0
Example with 2 IN data banks
SW
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
write data from CPU
BANK 0
SW
IN
DATA
(bank 1)
ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
NAK
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AT85C51SND3B2-RTTUL 功能描述:音频 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube
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