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参数资料
| 型号： | AT85C51SND3B1-7FTUL |
| 厂商： | Atmel |
| 文件页数： | 15/119页 |
| 文件大小： | 0K |
| 描述： | IC DECODER/ENCODER DGTL 100CBGA |
| 标准包装： | 90 |
| 类型： | 音频编码器/解码器 |
| 应用： | 移动电话，手机，视频显示器 |
| 电压 - 电源，数字： | 1.65 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TFBGA |
| 供应商设备封装： | 100-CTBGA（9x9） |
| 包装： | 托盘 |
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111
AT85C51SND3B
7632D–MP3–01/07
The CPU can free the bank by clearing FIFOCON when all the data are written, that
is:
–
after “N” write into UEDATX
–
as soon as RWAL is cleared by hardware.
If the endpoint uses 2 banks, the second one can be read by the HOST while the current
is being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may
be already ready (free) and TXINI is set immediately.
Standard Mode with AUTOSW
In this mode (AUTOSW set), the flow operation is the same as Section “Standard Mode
without AUTOSW”, page 110, with the exception that the CPU does not have to free the
bank (FIFOCON cleared): this will automatically be done when the CPU fills the bank.
EPINTx (TXINE set, TXINI set) or polling on TXINI=1 or FIFOCON=1,
The CPU acknowledges the interrupt by clearing TXINI,
The CPU can write the data to the current bank (write in UEDATX) while RWAL is
set.
A clear of FIFOCON does not have any effects in this mode.
Using the DFC with AUTOSW
In this mode (AUTOSW set, DFC programmed), the data are handled by the DFC with-
out any intervention from the CPU. The flow is:
programming of the DFC,
poll End Of Transfer from the DFC.
The bank switching is automatically done: when a bank is filled, it is freed and the switch
occurs. If the End Of Transfer occurs while the bank is not filled, the CPU has the
responsibility to free it.
The CPU shall not use UEDATX or the byte counter BYCT in this mode. A clear of
FIFOCON does not have any effects in this mode.
Using the DFC without
AUTOSW
In this mode (AUTOSW=0, DFC programmed), the data are handled by the DFC but the
CPU have to acknowledge each bank written:
programming of the DFC,
EPINTx (TXINE set, TXINI set) or polling on TXINI=1 or FIFOCON=1,
The CPU acknowledges the interrupt by clearing TXINI,
poll the wait of the transfer: (while RWAL is set: wait),
Clear FIFOCON which frees the bank and switch to the next one.
Abort
An “abort” stage can be produced by the host in some situations:
In a control transaction: ZLP data OUT received during a IN stage,
In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint
during a IN stage on the IN endpoint
…
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort
is to perform the following operations:
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相关代理商/技术参数 |
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| AT85C51SND3B1N-DDV | 功能描述:音频 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| AT85C51SND3B1N-RTTUL | 功能描述:音频 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| AT85C51SND3B1-RTTUL | 功能描述:音频 DSP MP3/WMA USB2.0 w/o DAC+DC/DC RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| AT85C51SND3B2-RTTUL | 功能描述:音频 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| AT85C51SND3BX | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:MP3 Microcontrollers |
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