B80547RE061256 PDF资料下载(40/94 页)32-BIT, 2530 MHz, MICROPROCESSOR, PBGA775

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参数资料

型号：	B80547RE061256
厂商：	INTEL CORP
元件分类：	微控制器/微处理器
英文描述：	32-BIT, 2530 MHz, MICROPROCESSOR, PBGA775
封装：	FLIP CHIP, LGA-775
文件页数：	40/94页
文件大小：	2796K
代理商：	B80547RE061256

Land Listing and Signal Descriptions

Datasheet

45

D27#

G13

Source Synch

Input/Output

D28#

F14

Source Synch

Input/Output

D29#

G14

Source Synch

Input/Output

D30#

F15

Source Synch

Input/Output

D31#

G15

Source Synch

Input/Output

D32#

G16

Source Synch

Input/Output

D33#

E15

Source Synch

Input/Output

D34#

E16

Source Synch

Input/Output

D35#

G18

Source Synch

Input/Output

D36#

G17

Source Synch

Input/Output

D37#

F17

Source Synch

Input/Output

D38#

F18

Source Synch

Input/Output

D39#

E18

Source Synch

Input/Output

D40#

E19

Source Synch

Input/Output

D41#

F20

Source Synch

Input/Output

D42#

E21

Source Synch

Input/Output

D43#

F21

Source Synch

Input/Output

D44#

G21

Source Synch

Input/Output

D45#

E22

Source Synch

Input/Output

D46#

D22

Source Synch

Input/Output

D47#

G22

Source Synch

Input/Output

D48#

D20

Source Synch

Input/Output

D49#

D17

Source Synch

Input/Output

D50#

A14

Source Synch

Input/Output

D51#

C15

Source Synch

Input/Output

D52#

C14

Source Synch

Input/Output

D53#

B15

Source Synch

Input/Output

D54#

C18

Source Synch

Input/Output

D55#

B16

Source Synch

Input/Output

D56#

A17

Source Synch

Input/Output

D57#

B18

Source Synch

Input/Output

D58#

C21

Source Synch

Input/Output

D59#

B21

Source Synch

Input/Output

D60#

B19

Source Synch

Input/Output

D61#

A19

Source Synch

Input/Output

D62#

A22

Source Synch

Input/Output

D63#

B22

Source Synch

Input/Output

DBI0#

A8

Source Synch

Input/Output

DBI1#

G11

Source Synch

Input/Output

DBI2#

D19

Source Synch

Input/Output

DBI3#

C20

Source Synch

Input/Output

DBR#

AC2

Power/Other

Output

DBSY#

B2

Common Clock

Input/Output

DEFER#

G7

Common Clock

Input

Table 4-1. Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

DP0#

J16

Common Clock

Input/Output

DP1#

H15

Common Clock

Input/Output

DP2#

H16

Common Clock

Input/Output

DP3#

J17

Common Clock

Input/Output

DRDY#

C1

Common Clock

Input/Output

DSTBN0#

C8

Source Synch

Input/Output

DSTBN1#

G12

Source Synch

Input/Output

DSTBN2#

G20

Source Synch

Input/Output

DSTBN3#

A16

Source Synch

Input/Output

DSTBP0#

B9

Source Synch

Input/Output

DSTBP1#

E12

Source Synch

Input/Output

DSTBP2#

G19

Source Synch

Input/Output

DSTBP3#

C17

Source Synch

Input/Output

EDRDY#1

F2

Common Clock

Input

FERR#/PBE#

R3

Asynch GTL+

Output

GTLREF_SEL

H29

Power/Other

—

GTLREF0

H1

Power/Other

Input

GTLREF1

H2

—

HIT#

D4

Common Clock

Input/Output

HITM#

E4

Common Clock

Input/Output

IERR#

AB2

Asynch GTL+

Output

IGNNE#

N2

Asynch GTL+

Input

INIT#

P3

Asynch GTL+

Input

ITP_CLK0

AK3

TAP

Input

ITP_CLK1

AJ3

TAP

Input

LINT0

K1

Asynch GTL+

Input

LINT1

L1

Asynch GTL+

Input

LL_ID0

V2

Power/Other

Output

LL_ID1

AA2

Power/Other

Output

LOCK#

C3

Common Clock

Input/Output

MCERR#

AB3

Common Clock

Input/Output

MS_ID0

W1

Power/Other

Output

MS_ID1

V1

Power/Other

Output

PC_REQ#1

G5

Common Clock

Output

PROCHOT#

AL2

Asynch GTL+

Input/Output

PWRGOOD

N1

Power/Other

Input

REQ0#

K4

Source Synch

Input/Output

REQ1#

J5

Source Synch

Input/Output

REQ2#

M6

Source Synch

Input/Output

REQ3#

K6

Source Synch

Input/Output

REQ4#

J6

Source Synch

Input/Output

RESERVED

A20

—

RESERVED

AC4

—

RESERVED

AE3

—

Table 4-1. Alphabetical Land

Assignments

Land Name

Land

#

Signal Buffer

Type

Direction

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