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参数资料
| 型号： | B80547RE061256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2530 MHz, MICROPROCESSOR, PBGA775 |
| 封装： | FLIP CHIP, LGA-775 |
| 文件页数： | 63/94页 |
| 文件大小： | 2796K |
| 代理商： | B80547RE061256 |
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66
Datasheet
Land Listing and Signal Descriptions
GTLREF_SEL
Output
GTLREF_SEL is used to select the appropriate chipset GTLREF voltage.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any FSB agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be continued by
reasserting HIT# and HITM# together.
IERR#
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system
core logic. The processor will keep IERR# asserted until the assertion of
RESET#.
This signal does not have on-die termination. Refer to Section 2.5 for
termination requirements.
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore
a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is de-asserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous floating-
point instruction caused an error. IGNNE# has no effect when the NE bit in
control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an input/output write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus
transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-point registers.
The processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal and must connect the appropriate pins/lands of all processor FSB
agents.
If INIT# is sampled active on the active to inactive transition of RESET#,
then the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0]
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0]
are used as BCLK[1:0] references for a debug port implemented on an
interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are
no connects in the system. These are not processor signals.
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of
all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1 becomes
NMI, a nonmaskable interrupt. INTR and NMI are backward compatible
with the signals of those names on the Pentium processor. Both signals are
asynchronous.
Both of these signals must be software configured via BIOS programming
of the APIC register space to be used either as NMI/INTR or LINT[1:0].
Because the APIC is enabled by default after Reset, operation of these
signals as LINT[1:0] is the default configuration.
LL_ID[1:0]
Output
The LL_ID[1:0] signals are used to select the correct loadline slope for the
processor.
Table 4-3. Signal Description (Sheet 5 of 9)
Name
Type
Description
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