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参数资料
| 型号： | BU-65843F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 22/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65843F3-200 |
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29
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
XQF
POINTER
XX00h
(part of) BC INSTRUCTION LIST
MESSAGE
CONTROL/STATUS
BLOCK 0
DATA BLOCK 0
XX10h
MESSAGE
CONTROL/STATUS
BLOCK 1
DATA BLOCK 1
POINTER
FIGURE 4. EXECUTE and FLIP (XQF) OPERATION
The third word in the message control/status block is a pointer
that references the first word of the message's data word block.
Note that the data word block stores only data words, which are
to be either transmitted or received by the BC. By segregating
data words from command words, status words, and other con-
trol and "housekeeping" functions, this architecture enables the
use of convenient, usable data structures, such as circular
buffers and double buffers.
Other operations support program flow control; i.e., jump and call
capability. The call capability includes maintenance of a call stack
which supports a maximum of four (4) entries; there is also a
return instruction. In the case of a call stack overrun or underrun,
the BC will issue a CALL STACK POINTER REGISTER ERROR
interrupt, if enabled.
Other op codes may be used to delay for a specified time; start a new
BC frame; wait for an external trigger to start a new frame; perform
comparisons based on frame time and time-to-next message; load
the time tag or frame time registers; halt; and issue host interrupts. In
the case of host interrupts, the message control processor passes a
4-bit user-defined interrupt vector to the host, by means of the PCI
Mini-ACE Mark3/Micro-ACE TE's Interrupt Status Register.
The purpose of the FLG instruction is to enable the message
sequence controller to set, clear, or toggle the value(s) of any or
all of the eight general purpose condition flags.
The op code parity bit encompasses all sixteen bits of the op
code word. This bit must be programmed for odd parity. If the
message sequence control processor fetches an undefined op
code word, an op code word with even parity, or bits 9-5 of an op
code word do not have a binary pattern of 01010, the message
sequence control processor will immediately halt the BC's oper-
ation. In addition, if enabled, a BC TRAP OP CODE interrupt will
be issued. Also, if enabled, a parity error will result in an OP
CODE PARITY ERROR interrupt. TABLE 53 describes the
Condition Codes.
BC MESSAGE SEQUENCE CONTROL
The PCI Mini-ACE Mark3/Micro-ACE TE BC message sequence
control capability enables a high degree of offloading of the host
processor. This includes using the various timing functions to
enable autonomous structuring of major and minor frames. In
addition, by implementing conditional jumps and subroutine
calls, the message sequence control processor greatly simplifies
the insertion of asynchronous, or "out-of-band" messages.
Execute and Flip Operation. The PCI Mini-ACE Mark3/Micro-
ACE TE BC's XQF, or "Execute and Flip" operation, provides
some unique capabilities. Following execution of this uncondi-
tional instruction, if the condition code tests TRUE, the BC will
modify the value of the current XQF instruction's pointer para-
meter by toggling bit 4 of the pointer. That is, if the selected con-
dition flag tests true, the value of the parameter will be updated
to the value = old address XOR 0010h. As a result, the next time
that this line in the instruction list is executed, the Message
Control/Status Block at the updated address (old address XOR
0010h) will be processed, rather than the one at the old address.
The operation of the XQF instruction is illustrated in FIGURE 4.
There are multiple ways of utilizing the "execute and flip" instruc-
tion. One is to facilitate the implementation of a double buffering
data scheme for individual messages. This allows the message
sequence control processor to "ping-pong" between a pair of
data buffers for a particular message. By doing so, the host
processor can access one of the two Data Word blocks, while the
BC reads or writes the alternate Data Word block.
A second application of the "execute and flip" capability is in con-
junction with message retries. This allows the BC to not only
switch buses when retrying a failed message, but to automati-
cally switch buses permanently for all future times that the same
message is to be processed. This not only provides a high
degree of autonomy from the host CPU, but saves BC band-
width, by eliminating the need for future attempts to process
messages on an RT's failed channel.
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