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| 型号： | BU-65843F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 56/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65843F3-200 |
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6
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
INTRODUCTION
The BU-65743 RT, and BU-65843/65864 BC/RT/MT PCI Mini-
ACE Mark3/Micro-ACE TE family of MIL-STD-1553 terminals
comprise a complete integrated interface between a PCI host
processor and a MIL-STD-1553 bus.
All members of the PCI Mini-ACE Mark3 family are packaged in
the same 0.88" square, 80-lead CQFP package. All members of
the PCI Micro-ACE TE family are packaged in the same 0.8"
square, 324 ball, plastic BGA package.
The PCI Mini-ACE Mark3/Micro-ACE TE hybrid's provide soft-
ware compatibility with the Enhanced Mini-ACE, Mini-ACE (Plus)
terminals, as well as software compatibility with the older ACE
series.
The PCI Mini-ACE Mark3/Micro-ACE TE provides complete mul-
tiprotocol support of MIL-STD-1553A/B/McAir and STANAG
3838. All versions integrate dual transceivers; along with proto-
col, host interface, memory management logic; and a minimum
of 4K words of RAM. In addition, the BU-6586X BC/RT/MT ter-
minals include 64K words of internal RAM, with built-in parity
checking.
The PCI Mini-ACE Mark3s include a 3.3V or 5V voltage source
transceiver for improved line driving capability, with options for
MIL-STD-1760 and McAir compatibility. The PCI Micro-ACE TEs
are available with 3.3V or 5V voltage source transceivers but do
not offer a McAIR option. Please consult the ordering information
section at the end of this document for all available options.
To provide further flexibility, the PCI Mini-ACE Mark3/Micro-ACE
TE has internal 1553 master clock dividers that allow operation
with either 10, 12, 16, or 20 MHz clock inputs. The 1553 master
clock divider is software programmable or, in the case of the
Micro ACE TE, can be controlled via pins when the RTBoot
mode is strapped.
The PCI Mini-ACE Mark3/Micro-ACE TEs are fully compliant tar-
gets, as defined by the PCI Local Bus Specification Revision 2.2,
using a 32 bit interface that operates at clock speeds of up to 33
Mhz, from a 3.3V bus. The interface supports PCI interrupts and
contains a FIFO that handles PCI burst write transfer cycles. The
FIFO is deep enough to accept an entire 1553 message. The
PCI interface is NOT 5V tolerant and can not be used in a 5V PCI
signaling environment.
One of the salient features of the PCI Mini-ACE Mark3 is its
Enhanced Bus Controller architecture. The Enhanced BC's high-
ly autonomous message sequence control engine provides a
means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
TABLE 1 NOTES: (Cont.)
(16) The 5V tolerant pins are RTAD0-5, RTAD_PAR, RTAD_LAT,
TXINH_A/B,
SSFLAG*/EXT_TRIG,
TAG_CLK,
RTBOOT_L,
CLK_SEL_0 and CLK_SEL_1.
(17) Current drain and power dissipation specs are based upon a small
sampliing of 3.3V transceivers and are subject to change.
(18) Power dissipation is the input power minus the power delivered to
the 1553 fault isolation resistors, the power delivered to the bus ter-
mination resistors and the copper losses in the transceiver isolation
transformer and the bus coupling transformer.
(19) The effective input capacitance as seen from the 1553 bus is
reduced by the square of the turns ratio of the coupling transformer.
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