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参数资料
| 型号： | BU-65843F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 5/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65843F3-200 |
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13
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
0
31(MSB)
DESCRIPTION
BIT
TABLE 15. REG5 DISCARD TIMER PRELOAD
REGISTER (READ/WRITE 814H)
DISCARD TIMER VALUE - BIT 15 (MSB)
15
0
16
DISCARD TIMER VALUE - BIT 0 (LSB)
0 (LSB)
DISCARD TIMER VALUE: Write this register to set the value to
be used for the discard timer. The default value is "0". The default
value meets the PCI spec and no access to this register is need-
ed for normal applications.
RESERVED - BIT 31 (MSB)
31(MSB)
DESCRIPTION
BIT
TABLE 16. REG6 GENERAL PURPOSE REGISTER
(READ/WRITE 818H)
RESERVED - BIT 0 (LSB)
0 (LSB)
This register will be all 0s after RST#. This read/write register is
available for customer use, perhaps as a flag register for signal-
ing between bus masters.
RESERVED, WRITE AS 0 - BIT 31 (MSB)
31(MSB)
DESCRIPTION
BIT
TABLE 17. REG7 RESERVED REGISTER
(WRITE 81CH)
RESERVED - BIT 0 (LSB)
0 (LSB)
CLEAR FAILSAFE INTERRUPT
1
This register will be all 0s after RST#. No access to this register
is needed for normal applications.
BITS 31-2 ARE RESERVED AND MUST BE WRITTEN AS 0s
CLEAR FAILSAFE INTERRUPT: Clears the Failsafe Interrupt
when set to "1". Failsafe interrupts can also be cleared via the
Failsafe Interrupt Autoclear mechanism, enabled by bit 18 in Reg
1.
ACE RESET: Resets the ACE when set to "1".
PCI MINI-ACE MARK3/MICRO-ACE TE REGISTER AND
MEMORY ADDRESSING
The software interface of the enhanced Mini-ACE portion of the
PCI mini-ACE Mark3/Micro ACE TE to the host processor con-
sists of 24 internal operational registers for normal operation, an
additional 24 test registers, plus 64K words of shared memory
address space. The PCI Mini-ACE Mark3/Micro-ACE TE's 4K X
16 or 64K X 17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (internal address 00-1F).
The next 32 locations (internal address 20-3F) should be
reserved, since many of these are used for factory test.
INTERNAL REGISTERS
The internal address mapping, with the corresponding PCI BAR1
address offset, for the PCI Mini-ACE Mark3/Micro-ACE TE regis-
ters is illustrated in TABLE 18. Note that the address lines shown
are the PCI Mini-ACE Mark3/Micro-ACE TE's internal ACE reg-
ister bus and are left shifted 2 bits with respect to the PCI
address: A0 = PCI A2, A1 = PCI A3, etc. For example, Interrupt
mask register #1 is located at PCI address BAR1 offset + 0h,
Configuration Register #1 is at BAR1 offset + 4h, etc. Note that
the table below does not show the internal A5 register address
line, which is normally 0 and is set only for access to the
reserved factory test registers.
Also note that the ACE registers are internally 16 bits wide,
appear in the lower 16 bits of a 32-bit PCI DWord and that the
upper 16 bits will read as zeroes during a 32bit PCI read.
The configuration registers will be cleared to 0000h after hard-
ware or software reset, with the exception of the Enhanced CPU
Access bit (bit 14 in Configuration register #6).
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