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参数资料
| 型号： | BU-65843F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 35/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65843F3-200 |
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40
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
ACE TE monitor writes messages to the lower half of the stack.
Later, when the monitor issues a 100% stack rollover interrupt, the
host can proceed to read the received data from the lower half of
the stack, while the PCI Mini-ACE Mark3/Micro-ACE TE monitor
continues to write received data words to the upper half of the
stack.
INTERRUPT STATUS QUEUE
Like the PCI Mini-ACE Mark3/Micro-ACE TE RT, the Selective
Monitor mode includes the capability for generating an interrupt
status queue. As illustrated in FIGURE 9, this provides a chrono-
logical history of interrupt generating events. Besides the two
Interrupt Mask Registers, the Interrupt Status Queue provides
additional filtering capability, such that only valid messages
and/or only invalid messages may result in entries to the Interrupt
Status Queue. The interrupt status queue is 64 words deep, pro-
viding the capability to store entries for up to 32 monitored mes-
sages.
MISCELLANEOUS
1553 CLOCK INPUT
The PCI Mini-ACE Mark3/Micro-ACE TE decoder is capable of
operating from a 10, 12, 16, or 20 MHz clock input. The clock fre-
quency may be specified by means of the host processor writing
to Configuration Register #6. In addition when PCI Micro-ACE TE
parts have their RTBOOT_L ball asserted, the 1553 input clock
divider is controlled by the CLK_SEL 0 and CLK_SEL_1 balls.
ENCODER/DECODERS
For the selected clock frequency, there is internal logic to derive
the necessary clocks for the Manchester encoder and decoders.
For all clock frequencies, the decoders sample the receiver out-
puts on both edges of the input clock. By in effect doubling the
decoders' sampling frequency, this serves to widen the tolerance
to zero-crossing distortion, and reduce the bit error rate.
TIME TAG
The PCI Mini-ACE Mark3/Micro-ACE TE includes an internal
read/writable Time Tag Register. This register is a CPU
read/writable 16-bit counter with a programmable resolution of
either 2, 4, 8, 16, 32, or 64 ms per LSB. In addition, this register
can be incremented directly by the TAG_CLK input pin by writing
all ones to the time tag resolution bits. Another option allows soft-
ware controlled incrementing of the Time Tag Register. This sup-
ports self-test for the Time Tag Register. For each message
processed, the value of the Time Tag Register is loaded into the
second location of the respective descriptor stack entry ("TIME
TAG WORD") for BC/RT/MT modes.
The functionality of the Time Tag Register is compatible with
ACE/Mini-ACE (Plus) includes: the capability to issue an inter-
rupt request and set a bit in the Interrupt Status Register when
the Time Tag Register rolls over FFFF to 0000; for RT mode, the
capability to automatically clear the Time Tag Register following
reception of a Synchronize (without data) mode command, or to
load the Time Tag Register following a Synchronize (with data)
mode command.
Additional time tag features supported by the PCI Mini-ACE
Mark3/Micro-ACE TE include the capability for the BC to transmit
the contents of the Time Tag Register as the data word for a
Synchronize (with data) mode command; the capability for the
RT to "filter" the data word for the Synchronize with data mode
command, by only loading the Time Tag Register if the LSB of
the received data word is "0"; an instruction enabling the BC
Message Sequence Control engine to autonomously load the
Time Tag Register with a specified value; and an instruction
enabling the BC Message Sequence Control engine to write the
value of the Time Tag Register to the General Purpose Queue.
INTERRUPTS
The PCI Mini-ACE Mark3/Micro-ACE TE series terminals provide
many programmable options for interrupt generation and han-
dling. The interrupt output pin (INT) has two software program-
mable modes of operation: a level output cleared under software
control, or a level output automatically cleared following a read of
the Interrupt Status Register (#1 or #2).
Individual interrupts are enabled by the two Interrupt Mask
Registers. The host processor may determine the cause of the
interrupt by reading the two Interrupt Status Registers, which
provide the current state of interrupt events and conditions. The
Interrupt Status Registers may be updated in two ways. In one
interrupt handling mode, a particular bit in Interrupt Status
Register #1 or #2 will be updated only if the event occurs and the
corresponding bit in Interrupt Mask Register #1 or #2 is enabled.
In the enhanced interrupt handling mode, a particular bit in one
of the Interrupt Status Registers will be updated if the event/con-
dition occurs regardless of the value of the corresponding
Interrupt Mask Register bit. In either case, the respective
Interrupt Mask Register (#1 or #2) bit is used to enable an inter-
rupt for a particular event/condition.
Monitor Command Stack Pointer B (fixed location)
Monitor Data Stack A
0800-0FFF
Monitor Command Stack A
0400-07FF
Not Used
0300-03FF
Selective Monitor Lookup Table
0280-02FF
Not Used
0108-027F
Monitor Data Stack Pointer B (fixed location)
0107
Not Used
0104-0105
Monitor Data Stack Pointer A (fixed location)
0103
Monitor Command Stack Pointer A (fixed location)
0102
Not Used
0100-0101
DESCRIPTION
ADDRESS
(HEX)
0106
TABLE 61. TYPICAL SELECTIVE MESSAGE
MONITOR MEMORY MAP (shown for 4K RAM for
“Monitor only” mode)
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