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参数资料
| 型号： | BX80532KC3000D |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 3000 MHz, MICROPROCESSOR |
| 文件页数： | 10/129页 |
| 文件大小： | 1640K |
| 代理商： | BX80532KC3000D |
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Intel Xeon Processor with 512 KB L2 Cache
Datasheet
107
7.4.2
Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which may be
used for other data at the system or processor vendor’s discretion. The data in this EEPROM, once
programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a
weak pull-down (10 kW) to allow the EEPROM to be programmed in systems with no
implementation of this signal. The Scratch EEPROM resides in the upper half of the memory
component (addresses 80 - FFh). The lower half comprises the Processor Information ROM
(address 00 - 7Fh), which is permanently write protected by Intel.
7.4.3
PIROM and Scratch EEPROM Supported SMBus Transactions
The Processor Information ROM (PIR) responds to two SMBus packet types: Read Byte and Write
Byte. However, since the PIR is write-protected, it will acknowledge a Write Byte command but
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands. Table 45
diagrams the Read Byte command. Table 46 diagrams the Write Byte command. Following a write
cycle to the scratch ROM, software must allow a minimum of 10ms before accessing either ROM
of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit,
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In
the tables the data addresses indicate 8 bits.The SMBus host controller should transmit 8 bits with
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
7.4.4
SMBus Thermal Sensor
The processor’s SMBus thermal sensor provides a means of acquiring thermal data from the
processor. The thermal sensor is composed of control logic, SMBus interface logic, a precision
analog-to-digital converter, and a precision current source. The sensor drives a small current
through the p-n junction of a thermal diode located on the processor core. The forward bias voltage
generated across the thermal diode is sensed and the precision A/D converter derives a single byte
of thermal reference data, or a “thermal byte reading.” The nominal precision of the least
significant bit of a thermal byte is 1 °C.
The processor incorporates the SMBus thermal sensor and thermal reference byte onto the
processor package as was previously done on Intel
Xeon processor family. Upper and lower
thermal reference thresholds can be individually programmed for the SMBus thermal sensor.
Comparator circuits sample the register where the single byte of thermal data (thermal byte
Table 45. Read Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
AS
Slave
Address
Rea
d
A
Data
///
P
17-bits
1
18-bits
1
7-bits
1
8-bits
1
Table 46. Write Byte SMBus Packet
S
Slave
Address
Write
A
Command Code
AData
AP
17-bits
1
18-bits
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80532KC3000H | 制造商:Intel 功能描述:MPU XEON NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KE2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KE2000DU | 制造商:Intel 功能描述:XEON 2.0GHZ 533FSB 1U - Boxed Product (Development Kits) |
| BX80532KE2400DSL73L | 制造商:Intel 功能描述: |
| BX80532KE2400E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
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