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参数资料
| 型号： | BX80532KC3000D |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 3000 MHz, MICROPROCESSOR |
| 文件页数： | 38/129页 |
| 文件大小： | 1640K |
| 代理商： | BX80532KC3000D |
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Intel Xeon Processor with 512 KB L2 Cache
16
Datasheet
Care must be taken in the baseboard design to ensure that the voltage provided to the processor
remains within the specifications listed in Table 6. Failure to do so can result in timing violations or
reduced lifetime of the component. For further information and guidelines, refer to the appropriate
platform design guidelines.
2.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM
pins) to the 603-pin socket. Bulk decoupling may be provided on the voltage regulation module
(VRM) to meet help meet the large current swing requirements. The remaining decoupling is
provided on the baseboard. The power delivery path must be capable of delivering enough current
while maintaining the required tolerances (defined in Table 6). For further information regarding
power delivery, decoupling, and layout guidelines, refer to the appropriate platform design
guidelines.
2.3.2
Front Side Bus AGTL+ Decoupling
The Intel Xeon processor with 512 KB L2 cache integrates signal termination on the die as well
as part of the required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly decouple the
return currents from the front side bus. Bulk decoupling must also be provided by the baseboard for
proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform
design guidelines.
2.4
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a multiple of the
BCLK[1:0] frequency. The maximum processor bus ratio multiplier will be set during
manufacturing. The default setting will equal the maximum speed for the processor.
The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate.
Clock multiplying within the processor is provided by the internal PLL, which requires a constant
frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC
specifications must be met while also meeting signal integrity requirements as outlined in Chapter
3.0. The processor utilizes a differential clock. Details regarding BCLK[1:0] driver specifications
are provided in the CK00 Clock Synthesizer/Driver Design Guidelines. Table 1 contains the
supported bus fraction ratios and their corresponding core frequencies.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80532KC3000H | 制造商:Intel 功能描述:MPU XEON NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KE2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
| BX80532KE2000DU | 制造商:Intel 功能描述:XEON 2.0GHZ 533FSB 1U - Boxed Product (Development Kits) |
| BX80532KE2400DSL73L | 制造商:Intel 功能描述: |
| BX80532KE2400E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
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