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参数资料
| 型号： | BX80532KE2000D |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2000 MHz, MICROPROCESSOR, XMA |
| 文件页数： | 21/102页 |
| 文件大小： | 1464K |
| 代理商： | BX80532KE2000D |
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Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz
25
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. VHavg is the statistical average of the VH measured by the oscilloscope.
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.
10.
VCROSS is defined as the total variation of all crossing voltages as defined in note 2.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
3. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4. VIH and VON may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
5. Refer to the IntelXeon Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V
characteristics.
6. The VCC referred to in these specifications refers to instantaneous VCC.
7. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with RTT enabled.
8. Leakage to VCC with pin held at 300 mV.
9. Leakage to VSS with pin held at VCC.
Table 9. TAP and PWRGOOD Signal Group DC Specifications
Table 8. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1,7
VIH
Input High Voltage
1.10 * GTLREF
VCC
V
2, 4, 6
VIL
Input Low Voltage
0.0
0.90 * GTLREF
V
3, 6
VOH
Output High Voltage
N/A
VCC
V4, 6
IOL
Output Low Current
N/A
VCC /
(0.50 * RTT_min + RON_min)
= 50
mA
6
IHI
Pin Leakage High
N/A
100
A
9
ILO
Pin Leakage Low
N/A
500
A
8
RON
Buffer On Resistance
7
11
5, 7
Symbol
Parameter
Min
Max
Unit
Notes 1, 2
VHYS
TAP Input Hysteresis
200
300
8
VT+
TAP input low to high
threshold voltage
0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX)5
VT-
TAP input high to low
threshold voltage
0.5 * (VCC - VHYS_MAX) 0.5 * (VCC - VHYS_MIN)5
VOH
Output High Voltage
N/A
VCC
V3, 5
IOL
Output Low Current
40
mA
6, 7
IHI
Pin Leakage High
N/A
100
A
10
ILO
Pin Leakage Low
N/A
500
A
9
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