- 您现在的位置：买卖IC网 > PDF目录210366 > BX80532KE2000D (INTEL CORP) 32-BIT, 2000 MHz, MICROPROCESSOR, XMA PDF资料下载
参数资料
| 型号： | BX80532KE2000D |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2000 MHz, MICROPROCESSOR, XMA |
| 文件页数： | 66/102页 |
| 文件大小： | 1464K |
| 代理商： | BX80532KE2000D |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页当前第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页
66
Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all processor clocks and power supplies are stable and within
their specifications. “Clean” implies that the signal will remain low (capable of
sinking leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. Figure 6 illustrates the relationship of PWRGOOD to
the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification in Table 13, and be followed
by a 1 mS RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
3
REQ[4:0]#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
front side bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking
of these signals.
4
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCC and BCLK
have reached their proper specifications. On observing active RESET#, all front
side bus agents will deassert their outputs within two clocks. RESET# must not be
kept asserted for more than 10ms.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
4
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor front side bus agents.
4
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor front side bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
4
SKTOCC#
O
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate
that the processor is present.
SLP#
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in
this state will not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
3
SMB_PRT
I
Pin is grounded on processor packages that do not contain SMBUS components
(PIROM, Scratch EEPROM, and thermal sensor). It is floating on processor
packages that contain the SMBus components.
Table 41. Signal Definitions (Sheet 7 of 9)
Name
Type
Description
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| BX80532KC1900E | 1900 MHz, MICROPROCESSOR |
| BU-61582D0-290S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D0-300K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-391Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-410S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80532KE2000DU | 制造商:Intel 功能描述:XEON 2.0GHZ 533FSB 1U - Boxed Product (Development Kits) |
| BX80532KE2400DSL73L | 制造商:Intel 功能描述: |
| BX80532KE2400E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KE2400EU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KE2667D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.66GHZ - Boxed Product (Development Kits) |
发布紧急采购，3分钟左右您将得到回复。