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| 型号： | BX805555080A |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封装： | LGA-771 |
| 文件页数： | 87/104页 |
| 文件大小： | 3690K |
| 代理商： | BX805555080A |
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Dual-Core Intel Xeon Processor 5000 Series Datasheet
83
Features
7
Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Dual-Core Intel Xeon
Processor 5000 series samples its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifics on these options, please refer to Table 7-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor, for reset configuration purposes, the processor does not distinguish
between a “warm” reset (PWRGOOD signal remains asserted during reset) and a
“power-on” reset.
Notes:
1.
Asserting this signal during RESET# will select the corresponding option.
2.
Address pins not identified in this table as configuration options should not be asserted during RESET#.
3.
This mode is not tested.
7.2
Clock Control and Low Power States
The Dual-Core Intel Xeon Processor 5000 series support the Enhanced HALT
Powerdown state in addition to the HALT Powerdown state and Stop-Grant states to
reduce power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See Figure 7-1 for a visual representation of the
processor low power states.
The Enhanced HALT state is enabled by default in the Dual-Core Intel Xeon Processor
5000 series. The Enhanced HALT state must remain enabled via the BIOS for the
processor to remain within its specifications. For processors that are already running at
the lowest core to bus ratio for its nominal operating point, the processor will transition
to the HALT Powerdown state instead of the Enhanced HALT state.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. The Hyper-Threading Technology feature adds the
conditions that all logical processors share the same STPCLK# signal internally. When
the STPCLK# signal is asserted, the processor enters the Stop Grant state, issuing a
Stop Grant Special Bus Cycle (SBC) for each processor or logical processor. The chipset
Table 7-1.
Power-On Configuration Option Lands
Configuration Option
Land Name
Notes
Output tri state
SMI#
1,2
Execute BIST (Built-In Self Test)
A3#
1,2
In Order Queue de-pipelining (set IOQ depth to
1)
A7#
1,2
Disable MCERR# observation
A9#
1,2
Disable BINIT# observation
A10#
1,2
Disable bus parking
A15#
1,2
Symmetric agent arbitration ID
BR[1:0]#
1,2
Force single logical processor
A31#
1,2,3
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