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参数资料
| 型号： | DAC5687IPZP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 20/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZP |
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Register Name: CONFIG3—Address: 0x04, Default = 0x00
Register Name: SYNC_CNTL—Address: 0x05, Default = 0x00
Register Name: SER_DATA_0—Address: 0x06, Default = 0x00
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
BIT 7
BIT 0
sif_4pin
dac_ser_data
half_rate
unused
usb
counter_mode(2:0)
0
sif_4pin: Four-pin serial interface mode is enabled when set, three-pin mode when cleared.
dac_ser_data: When set, both DAC A and DAC B input data is replaced with fixed data loaded into the 16-bit
serial interface ser_data register.
half_rate: Enables half-rate input mode. Input data for the DAC A data path is input to the chip at half speed
using both the DA[15:0] and DB[15:0] input pins.
usb: When set, the data to DACB is inverted to generate upper-sideband output.
counter_mode(2:0): Controls the internal counter that can be used as the DAC data source. Replaces digital
values at DACs with a cyclic counter.
{0XX = off; 100 = all 16b; 101 = 7b LSBs; 110 = 5b MIDs; 111 = 5b MSBs}
BIT 7
BIT 0
sync_phstr
sync_nco
sync_cm
sync_fifo(2:0)
unused
0
sync_phstr: When set, the internal clock divider logic is initialized with a PHSTR pin low-to-high transition.
sync_nco: When set, the NCO phase accumulator is cleared with a PHSTR low-to-high transition.
sync_cm: When set, the coarse mixer is initialized with a PHSTR low-to-high transition.
sync_fifo(2:0): Sync source selection mode for the FIFO. When a low-to-high transition is detected on the
selected sync source, the FIFO input and output pointers are initialized.
Table 4. Synchronization Source
sync_fifo(2:0)
Synchronization Source
000
TXENABLE pin
001
PHSTR pin
010
QFLAG pin
011
DB[15]
100
DA[15] first transition (one shot)
101
Software sync using SIF write
110
Sync source disabled (always off)
111
Always on
BIT 7
BIT 0
dac_data(7:0)
0
dac_data(7:0): Lower 8 bits of DAC data input to the DACs when dac_ser_data is set.
Copyright 2005–2006, Texas Instruments Incorporated
27
Product Folder Link(s): DAC5687
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| DAC5687IPZPG4 | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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