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参数资料
| 型号： | DAC5687IPZP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 35/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZP |
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Σ
I
13
daca_offset
{–4096, –4095, ..., 4095}
B016501
Σ
Q
13
dacb_offset
{–4096, –4095, ..., 4095}
Analog DAC Gain
I
fullscale +
16 V
extio
R
BIAS
GAINCODE ) 1
16
B 1 *
FINEGAIN
3072
Clock Modes
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
During the four DAC clock cycles, the partially updated offset register values are summed to the DAC signal.
This can result in offset values during the first three DAC clock cycles that are significantly different from the
starting and ending offset values. For example, Table 11 shows the transition from offset value 1023 to 1025.
The bit changes in each clock cycle are in bold. As can be seen, the transition between 1023 and 1025 results in
offset values of 1023, 1279, and 1039 during the transition.
Table 11. Offset Values During Transition
DAC Clock Cycle
Signed Integer Value
Binary Format
Hexadecimal Format
0
1023 starting value
00 0011 1111 1111
0x03FF
1
1023
00 0011 1111 1111
0x03FF
2
1279
00 0100 1111 1111
0x04FF
3
1039
00 0100 0000 1111
0x040F
4
1025 ending value
00 0100 0000 0001
0x0401
Figure 42. DAC Offset Block
The full-scale DAC output current can be set by programming the daca_gain and dacb_gain registers. The DAC
gain value controls the full-scale output current.
where GAINCODE = daca_gain(11:8) or dacb_gain(11:8) is the coarse gain setting (0 to 15) and FINEGAIN =
daca_gain(7:0) or dacb_gain(7:0) (–128 to 127) is the fine gain setting.
In the DAC5687, the internal clocks (1
×, 2×, 4×, and 8× as needed) for the logic, FIR interpolation filters, and
DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or DAC output
sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) are separate from
the other clock generation blocks power (CLKVDD and CLKGND), thus minimizing phase noise within the PLL.
The DAC5687 has three clock modes for generating the internal clocks (1
×, 2×, 4×, and 8× as needed) for the
logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in register
CONFIG1.
40
Copyright 2005–2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687
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| DAC5687IPZPG4 | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687IPZPR | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687IPZPRG4 | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687MPZPEP | 功能描述:数模转换器- DAC 16B 500Msps 2X-8X Interp 2-Channel DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5688 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
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