参数资料
型号: DAC5687IPZP
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100
封装: GREEN, PLASTIC, HTQFP-100
文件页数: 46/79页
文件大小: 2490K
代理商: DAC5687IPZP
www.ti.com
T0155-01
PHSTR
clk_in
clk_out
phstratFIFO
Output
clk_cmix
Sequencer
fs/2
OnlyMustBeHighforOneclk_inPeriod
InputDelayLine+FIFODelay
0
180
90
0
180
0
180
90
270
0
Sequencer
fs/4
Sequencer
Reset
Input Clock Synchronization of Multiple DAC5687s
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 57. CMIX Reset Synchronization Timing
In addition to the reset function provided by the PHSTR signal, the phstr_del(1:0) bits in register ATEST allow
the user to select the initial (reset) state. Changing the cm_mode lower 2 bits produces the same phase shift
results.
Table 14. Initial State of CMIX After Reset
Fix Mix Selection
phstr_del(1:0)
Initial State at PHSTR
fS/2
00 and 10
Normal
fS/2
01 and 11
180-degree shift
fS/4
00
Normal
fS/4
01
90-degree shift
fS/4
10
180-degree shift
fS/4
11
270-degree shift
For applications where multiple DAC5687 chips are used, clock synchronization is best achieved by using
dual-clock mode with the FIFO disabled or the PLL-clock mode. In the dual-clock mode with FIFO disabled, an
appropriate clock PLL such as the CDC7005 is required to provide the DAC and input rate clocks that meet the
skew requirement talign (see Figure 47). An example for synchronizing multiple DAC5687 devices in dual clock
mode with two CDC7005s is shown in Figure 58. When using the internal PLL-clock mode, synchronization of
multiple using PHSTR is completely deterministic due to the phase/frequency detector in the PLL feedback loop.
All chips using the same CLK1/CLK1C input clock have identical internal clocking phases.
50
Copyright 2005–2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687
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