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| 型号： | DAC5687IPZP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 32/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZP |
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Quadrature Modulator Correction (QMC)
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Table 10. Coarse Mixer Sequences
cm_mode(3:0)
Mixing Mode
Sequence
00XX
No mixing
0100
fDAC/2
DAC A = {–A +A –A +A …}
DAC B = {–B +B –B +B …}
0101
fDAC/2
DAC A = {–A +A –A +A …}
DAC B = {+B –B +B –B …}
0110
fDAC/2
DAC A = {+A –A +A –A …}
DAC B = {–B +B –B +B …}
0111
fDAC/2
DAC A = {+A –A +A –A …}
DAC B = {+B –B +B –B …}
1000
fDAC/4
DAC A = {+A –B –A +B …}
DAC B = {+B +A –B –A …}
1001
fDAC/4
DAC A = {+A –B –A +B …}
DAC B = {–B –A +B +A …}
1010
fDAC/4
DAC A = {–A +B +A –B …}
DAC B = {+B +A –B –A …}
1011
fDAC/4
DAC A = {–A +B +A –B …}
DAC B = {–B –A +B +A …}
1100
–fDAC/4
DAC A = {+A +B –A –B …}
DAC B = {+B –A –B +A …}
1101
–fDAC/4
DAC A = {+A +B –A –B …}
DAC B = {–B +A +B –A …}
1110
–fDAC/4
DAC A = {–A –B +A +B …}
DAC B = {+B –A –B +A …}
1111
–fDAC/4
DAC A = {–A –B +A +B …}
DAC B = {–B +A +B –A …}
The output of CMIX is complex. For a real output, either DACA or DACB can be used and the other DAC slept,
the difference being the phase sequence.
The quadrature modulator correction (QMC) block provides a means for changing the phase balance of the
complex signal to compensate for I and Q imbalance present in an analog quadrature modulator. The QMC block
is limited in operation to a clock rate of 320 MSPS.
The block diagram for the QMC block is shown in Figure 40. The QMC block contains three programmable
parameters. Registers qmc_gain_a and qmc_gain_b control the I and Q path gains and are 11-bit values with a
range of 0 to approximately 2. Note that the I and Q gain can also be controlled by setting the DAC full-scale
output current (see following). Register qmc_phase controls the phase imbalance between I and Q and is a
10-bit value with a range of –1/2 to approximately 1/2.
LO feedthrough can be minimized by adjusting the DAC offset feature described as follows.
An example of sideband optimization using the QMC block and gain adjustment is shown in Figure 41. The QMC
phase adjustment in combination with the DAC gain adjustment can reduce the unwanted sideband signal from
~40 dBc to > 65 dBc.
Note that mixing in the CMIX block after the QMC correction destroys the I and Q phase compensation
information from the QMC block.
38
Copyright 2005–2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687
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