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| 型号： | DAC5687IPZP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 79/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZP |
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ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued)
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V (= 3.3 V for PLL
clock mode), IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 19.2 mA, external clock mode, 4:1 transformer output termination,
50-
doubly terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Single carrier, baseband, X4, PLL clock mode,
78.4
CLK1 = 122.88 MHz
Single carrier, baseband, X4, PLL clock mode,
78.5
CLK2 = 491.52 MHz
Single carrier, IF = 153.6 MHz, X4 CMIX, external clock
70.9
mode, CLK2 = 491.52 MHz
Two carrier, IF = 153.6 MHz, X4 CMIX, external clock
67.8
mode, CLK2 = 491.52 MHz
Four carrier, baseband, X4, external clock mode,
76.1
CLK2 = 491.52 MHz
ACLR(4)
Adjacent channel leakage ratio
dBc
Four carrier, IF = 92.16 MHz, X4L, external clock mode,
66.8
CLK2 = 491.52 MHz
Single carrier, IF = 153.6 MHz, X4 CMIX, external clock
72.2
mode, CLK2 = 491.52 MHz, DVDD = 2.1 V
Two carrier, IF = 153.6 MHz, X4 CMIX, external clock
69.3
mode, CLK2 = 491.52 MHz, DVDD = 2.1 V
Four carrier, baseband, X4, external clock mode,
68.5
CLK2 = 491.52 MHz, DVDD = 2.1 V
Four carrier, IF = 92.16 MHz, X4L, external clock mode,
66.3
CLK2 = 491.52 MHz, DVDD = 2.1 V
50-MHz offset, 1-MHz BW, single carrier, baseband,
92
X4, external clock mode, CLK2 = 491.52 MHz
50-MHz offset, 1-MHz BW, four carrier, baseband,
81
X4, external clock mode, CLK2 = 491.52 MHz
Noise floor
dBc
50-MHz offset, 1-MHz BW, single carrier, baseband,
88
X4, PLL clock mode, CLK1 = 122.88 MHz
50-MHz offset, 1-MHz BW, four carrier, baseband,
81
X4, PLL clock mode, CLK1 = 122.88 MHz
(4)
W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUTFS = 19.2 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS INTERFACE
VIH
High-level input voltage
2
3
V
VIL
Low-level input voltage
0
0.8
V
VIH
High-level input voltage
IOVDD = 1.8 V
1.26
V
VIL
Low-level input voltage
IOVDD = 1.8 V
0.54
V
IIH
High-level input current
–40
40
A
IIL
Low-level input current
–40
40
A
Input capacitance
5
pF
Iload = –100 A
IOVDD – 0.2
VOH
PLLLOCK, SDO, SDIO
V
Iload = –8 mA
0.8 IOVDD
Iload = 100 A
0.2
VOL
PLLLOCK, SDO, SDIO
V
Iload = 8 mA
0.22 IOVDD
External or dual-clock modes
0
250
Input data rate
MSPS
PLL clock mode
2.5
160
Copyright 2005–2006, Texas Instruments Incorporated
9
Product Folder Link(s): DAC5687
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